System-Verilog implementation of the ACDMA crossbar
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Updated
Nov 25, 2018 - SystemVerilog
System-Verilog implementation of the ACDMA crossbar
Reconfigurable network on chip architecture for accelerating stochastic models
A 2x2 mesh NoC compatible with AXI streaming interface
My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
Research based implementation of a genetic algorithm for routing 'flits' in an NoC
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
Network-on-Chip Simulation using Noxim
Researching on Multi/Many-core Power-gating based on Network-on-Chip
Vivado test IP for Hermes NoC Router
System-on-Chip Interconnection Network - Simulation Environment (front-end)
A Network-on-Chip for the System-of-Systems Era, Enabling mixed interface communication between embedded devices (MCU, sensors etc.) over a common protcol stack
Real-Time Network-on-chip Analysis and Simulation
GeNoC - Software implementation of the evolutionary computation method for the synthesis of quasi-optimal topologies for Networks-on-Chip
Convolutional Neural Networks for Verilog High-Level Synthesis
University assignment, will soon be refactored
Example of hardware trojan in a router detected with formal property verification
Introduction about Embedded systems lab, University of Florida
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