Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
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Updated
May 11, 2017 - Verilog
Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
Approximate layers - TensorFlow extension
idle game thingy.
Parameterized and 4-bit carry save multiplier design
Approximate Multipliers of 8bit and 16bit operands, built with approximate compressors.
Useful VHDL scripts for hardware description.
Different Multipliers code in VHDL and Comparison
Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method
Verilog Multiplier Implementation
Design and Analysis of an FPGA-based Wallace Multiplier.
Bingo game with score
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