Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV
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Updated
May 25, 2024 - SystemVerilog
Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV
HF-RISC SoC
Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.
This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.
This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Fork from PYNQ branch with fixes and modifications for Digilent Genesys Zu.
i2c-xiic driver with added support for master_xfer_atomic()
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