MPSoC-RISCV

QueenField

Multi-Processor System on Chip with ISA RISCV

Name		Name	Last commit message	Last commit date
Latest commit History 301 Commits
certification		certification
doc		doc
lifecycle		lifecycle
quality		quality
requirements		requirements
rtl		rtl
sim		sim
soc @ baa44f8		soc @ baa44f8
software		software
source		source
synthesis		synthesis
validation		validation
verification		verification
.gitmodules		.gitmodules
LICENSE		LICENSE
README.md		README.md
icon.jpg		icon.jpg
mpsoc-riscv.png		mpsoc-riscv.png
mpsoc-riscv.svg		mpsoc-riscv.svg
settings64_ghdl.bat		settings64_ghdl.bat
settings64_iverilog.bat		settings64_iverilog.bat
settings64_msim.bat		settings64_msim.bat
settings64_msim.sh		settings64_msim.sh
settings64_verilator.bat		settings64_verilator.bat
settings64_vivado.bat		settings64_vivado.bat
settings64_vivado.sh		settings64_vivado.sh
settings64_yosys.bat		settings64_yosys.bat
submodule.sh		submodule.sh
tag.sh		tag.sh
upload.sh		upload.sh