riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.
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Updated
Oct 26, 2020 - Coq
riscv_myth_workshop created by GitHub Classroom. Contains an implemented RISC-V 32-bit core.
Presentation about software-based Micro-architectural Side-Channel attacks.
Class project for ECE721: Advanced Microarchitecture. This project involves implementing a renamer class that uses AMT, RMT, Active List, Free List, and Physical Register File.
Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
Experiments with low level assembly language
Implements a BDP (Branch difference predictor) based on the paper by Timothy H Heil, Zak Smith and JE Smith - "Improving branch predictors by correlating on data values"
Fun with branch predictors
A System Verilog processor design of a single cycle MIPS architecture
A cross platform Redis Module Example that warns and uses the optimized functions based on instruction set extensions available and or microarchitecture
Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.
A runahead execution CPU model in the gem5 simulator - feat. delayed exit experiments
Repository for the course MO601 - Computer Architecture II
Simple TLB (Translation lookaside buffer) realization on verilog.
32-bit RISC-V microarchitecture with a three-stage pipeline
A simple computer architeture, ISA and Interpreter build with Rust.
high instruction-level-parallelism (ILP) using Resource-Flow-Execution
Register file cache implementation on the Marssx86 architectural simulator
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