learn the combinational and sequential logic circuit.
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Updated
May 26, 2024 - SystemVerilog
learn the combinational and sequential logic circuit.
HDL support for VS Code
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
Pre and Post Synthesis Simulation of a Design VSDMemSOC
This linter plugin for SublimeLinter provides an interface to iverilog (verilog compiler).
A collection of Verilog code snippets and assignments for computer science coursework.
IceChips is a library of all common discrete logic devices in Verilog
Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh,vscode 等开源工具链的开发环境。
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
This Repository contains my code for the Digital System Design (DSD) lab during my 3rd Semester of B.Tech.
Sample Verilog codes for digital circuits
VLIW architecture is an appropriate alternative for exploiting instruction-level parallelism (ILP) in programs. In this project 5 stage pipline and 6 functional unit is used.
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