Cardinal NIC and Chip Multiprocessor
-
Updated
Dec 1, 2021 - Verilog
#
innovus
Here are 4 public repositories matching this topic...
DLX microprocessor described in VHDL for the Microelectronic Systems course @ Politecnico di Torino
-
Updated
Jan 16, 2023 - Verilog
An application using Cadence IC Package
-
Updated
Feb 12, 2023 - Verilog
Detailed routed RT01 and other testcases with Innovus NanoRoute; includes RT01 random blockages. Example routes include CLK paths avoiding all blockages and connecting all DFF pins. All modules are designed with the GSCLK45nm standard cell library. Note that NanoRoute is typically used for routing std cell placements; in this case, custom top-level
-
Updated
Jul 16, 2023
Improve this page
Add a description, image, and links to the innovus topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the innovus topic, visit your repo's landing page and select "manage topics."