Peat, a Python-based Intel-Optimized Tensorflow dockerization with CPU & Memory constraints configurator
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Updated
Aug 5, 2020 - Python
Peat, a Python-based Intel-Optimized Tensorflow dockerization with CPU & Memory constraints configurator
Aureal A3D Software Development Kit
Machine Vision Cam Landing Page
Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
A collection of WebGPU samples.
Hardware Accelerator design for Euler and Modified method in solving ODE using VHDL language in Xilinx Vivado Environment
This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.
Convolutional Neural Networks for Verilog High-Level Synthesis
Aureal A3D Software Development Kit
Sudoku solver which uses hardware instruction set to speed up significantly the process
Digital Circuits Design Project (PoliMi, year 2022) - Memory Interaction
ZCU102 firmware. Package for enabling hardware acceleration capabilities in ROS 2 with ZCU102.
ZPrize 2022 - All qualified entries (Docker-backed fork)
Deep learning library that exports itself to HDL code for FPGA-based hardware acceleration
Just a simple and fast CRC32C Wrapper with hardware acceleration.
GLES offscreen rendering
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