My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.
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Updated
Feb 1, 2024 - C
My semester-long project for CS261 - Computer Systems at James Madison University where I constructed a cpu simulator using a smaller version of x86 called y86.
Basic VHDL projects gradually creating a pipelined CPU running Charis4 instruction set.
A 16 bit SAP-1 CPU that I designed in grade 10 designed in logisim
a smiple 8bit cpu implemented in verilog and tested on FPGA for understanding how CPU works
8-bit Harvard Architecture CPU implemented in ABEL
A custom CPU for an FPGA
16-bit CPU with specific Assembler for Assembly codes capable of controlling a 32x32 led screen
A repository of my assembly language learning journey, featuring programs that illustrate the core principles of microprocessor operations and low-level coding.
Trillek Virtual Computer specs
RTL code of an 8-bit CPU designed in Verilog with a separate file for each module.
Solutions for http://www.nand2tetris.org/
CPU Cache Simulation using gem5
Network-on-Chip Simulation using Noxim
Assembler and Simulator for RISC-V RV32I instruction set that runs entirely in web browser.
This is the Github repository containing all the VHDL files for the EE309 course project involving designing a 16-bit, 6-staged pipelined processor based on the RISC ISA.
The virtual CPU (and emulator) built for hobbyists
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