search engine simulator. Implement both the client and the server side, with emphasis on multithreaded programming and synchronization of these. Involves the use of sockets. server that efficiently handle large number of clients.

Simulator for queueing systems and LRU caches

A simulated cache system program. Test cache performance by dynamically specifying the cache structure to see how well optimized an algorithm is on different cache structures.

Memory hierarchy simulation, memory controller

Simulation of an Intel Kaby lake cache coded in C

Simulate cache behavior with this CacheSimulator, exploring cache policies, performance, and related concepts.

Computer architecture related projects

CSE 320 System Fundamentals II HW 5 - Caches

A reference implementation for time-homogeneous Markov chain based cache

Cache and memory hierarchy simulator using L1 or both L1 and L2 cache

Trabajos practicos de la materia Organizacion de computadoras 66.20 - 2C2020

Advanced Computer Architectures - Practical Assignment #2: Create a shell script that sends custom jobs (thread & core level parallelized code) to an SGE cluster scheduler in order to execute an HPC NPB Benchmark, so we can study the performance impact on a shared-memory multiprocessor when emulating different processor cache architectures (vary…

Simulation of a memory cache (addresses only), for Computer Architecture (2021-22).

Repository for college course IOAC projects.

This project provides tools to simulate several access strategies for distributed caching. The simulator considers a user who is equipped by several caches, and receives from them periodical updates about the cached content. These updates are not totally accurate. The user has to select which caches to access, to obtain the requested datum in th…

Exercise to make use of read-through pattern by building cache on top of db in GO.

Low-level programming assignments, "Low-Level Programming" (TDT4258) course, fall 2023.

A cache memory simulator implemented in C++, allowing users to simulate different cache configurations and analyze memory access patterns efficiently.