Simulate cache behavior, explore cache policies, and analyze performance.
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Table of Contents
The Cache Simulator project allows you to simulate cache behavior, analyze various cache policies, and evaluate performance. Use this tool to gain insights into caching strategies and optimize memory access patterns. This is an implementation of a write-through write-no-allocate cache policy for testing and educational purposes.
To get started with the Cache Simulator, follow the instructions below:
- Clone the repo
git clone https://github.com/wanghley/cache-simulator.git
- Compile the code
gcc -g -o cachesim cachesim.c
- Run the code
./cachesim <trace file.txt> <cache size in kB> <Associativity> <Block size in B>
This C program serves as a single-level cache simulator, providing a means to understand and analyze the behavior of a cache and the underlying memory system. It can be utilized in various scenarios to explore cache performance. The usage instructions and scenarios are outlined below:
To run the cache simulator, use the following command in the terminal:
./cachesim <filename> <cache size kB> <associativity> <block size B>Example:
./cachesim trace.txt 32 1 32<filename>: The name of the file containing memory access traces.<cache size kB>: Cache size in kilobytes.<associativity>: Cache associativity (number of ways).<block size B>: Block size in bytes.
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Memory Configuration:
- Addresses are 24 bits (3 bytes).
- Addressable memory ranges from 0 to 2^24 - 1 (16 MB).
- The machine is byte-addressable and big-endian.
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Cache Configuration:
- Cache size, associativity, and block size are powers of 2.
- Cache size is limited to 2MB, block size is limited to 1024B.
- No access is larger than the block size, and no access spans multiple blocks.
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Cache Operation:
- Cache is write-through and write-no-allocate.
- The cache is initially empty.
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Cache Access:
- For each memory access, the simulator outputs whether it's a cache hit or miss.
- If a miss occurs, the simulator loads the data from main memory.
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Supported Operations:
load: Reads data from cache or main memory.store: Writes data to cache or main memory.
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Cache Performance Analysis:
- Evaluate the impact of different cache configurations on hit/miss rates.
- Understand how changes in cache size, associativity, and block size affect performance.
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Memory Access Pattern Study:
- Analyze the behavior of the cache under different memory access patterns.
- Identify scenarios where cache locality is high or low.
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Cache Replacement Policy Testing:
- Observe the impact of cache replacement policies by analyzing cache hit/miss patterns.
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Teaching and Learning:
- Serve as an educational tool for students learning about computer architecture and cache systems.
- The program assumes a specific memory organization and cache policy, making it suitable for educational and analytical purposes.
- The debug mode (
DEBUG) can be enabled for additional output during execution.
Feel free to explore and modify the code to suit specific learning or analysis requirements.
- Implement basic cache simulation
- Add support for different cache policies
- Optimize code for performance
- Explore additional features based on user feedback
See the open issues for a full list of proposed features and known issues.
Contributions are welcome! If you have suggestions, improvements, or bug fixes, feel free to open an issue or submit a pull request.
- Fork the Project
- Create your Feature Branch (
git checkout -b feature/AmazingFeature) - Commit your Changes (
git commit -m 'Add some AmazingFeature') - Push to the Branch (
git push origin feature/AmazingFeature) - Open a Pull Request
Distributed under the MIT License. See LICENSE.txt for more information.
Wanghley Soares Martins - @wanghley - wanghley@wanghley.com
Project Link: https://github.com/your_username/CacheSimulator