bluespec
Here are 34 public repositories matching this topic...
Learning Bluespec on an iCEBreaker FPGA
-
Updated
May 12, 2024 - Bluespec
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
-
Updated
Feb 29, 2024 - Coq
Bluespec SystemVerilog extension for VS Code
-
Updated
Feb 6, 2024 - Bluespec
A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance
-
Updated
Dec 11, 2023 - Verilog
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
-
Updated
Sep 15, 2023 - Bluespec
Hardware implementation of Lightweight Cryptography candidates in Bluespec SystemVerilog.
-
Updated
Jun 29, 2023 - C
Bluespec System Verilog syntax highlighting for Notepad++
-
Updated
Jun 27, 2023
Forth CPU J1 in Bluespec SystemVerilog (BSV)
-
Updated
Apr 30, 2023 - Verilog
Wishbone/Bluespec Systemverilog Transactors
-
Updated
Feb 16, 2023 - Verilog
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
-
Updated
Oct 13, 2021 - Python
Domain Specific Hardware Accelerators - VLSI CAD Project
-
Updated
Jan 11, 2021 - Bluespec
RISC-V cores based on Bluespec's Piccolo and Flute
-
Updated
Jul 3, 2020 - Python
Improve this page
Add a description, image, and links to the bluespec topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the bluespec topic, visit your repo's landing page and select "manage topics."