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Client based system reset #200

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Client based system reset #200

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Commits on Apr 22, 2024

  1. First attempt at supporting host based reset 

    The feature enables the interface_rts signal from the CH552 MCU in
constraints as well as inte FPGA interface. The signal is routed into
the clk_reset_gen block where it is sampled. If the sampled signal is
set, a system reset is triggered

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
    @secworks @mchack-work
    secworks authored and mchack-work committed Apr 22, 2024
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  2. Trigger the original reset loop logic when host requests a reset 

    Add comments to explain function and clean up heade, footer

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
    @secworks @mchack-work
    secworks authored and mchack-work committed Apr 22, 2024
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  3. Move reset control and status into the tk1 core 

    The tk1 core is now able to handle external and internal reset
request, trigger a system and store reset status that persists
the reset. The reset status is exposed to SW as bits 17..16 in the
FW_APP register. The fw_app status is now bound to bit 0.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
    @secworks @mchack-work
    secworks authored and mchack-work committed Apr 22, 2024
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