Wolv Z3 CPU core

Wolv Z3 CPU core supports currently only riscv32-imcb instruction set architecture and is implemented with 3-stage pipeline and Harvard bus architecture.

Dhrystone Benchmark

Cycles	Dhrystone/s/MHz	DMIPS/s/MHz	Iteration
273	3658	2.08	1000

Coremark Benchmark

Cycles	Iteration/s/MHz	Iteration
287315	3.48	10

Documentation will be expanded in the future.