Wolv Z0 CPU core

Wolv Z0 CPU core supports currently only riscv32-imc instruction set architecture and is implemented with 2-stage pipeline and Neumann bus architecture.

Dhrystone Benchmark

Cycles	Dhrystone/s/MHz	DMIPS/s/MHz	Iteration
336	2889	1.69	1000

Coremark Benchmark

Cycles	Iteration/s/MHz	Iteration
349156	2.86	10

Documentation will be expanded in the future.