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shreegw/README.md

About Me

  • 👋 Hi, I’m Shree Ganesh, I am Currently pursuing Masters in Computer Engineering.
  • 👀 I’m interested in Hardware Security, Verilog, FPGAs, MCUs, SOCs, ICs, Embedded programming.
  • 🌱 I’m currently learning UVM, System Verilog, Computer Architecture, Cyber Physical Systems Security, Communication Protocols.
  • 💞️ I’m looking to collaborate on various FPGA projects
  • 📩 contact me

Github LinkedIn HDLBits

Verilog and FPGA Projects

Machine Learning Projects

Computer Organization and Architecture simulations and projects

Misc. Projects

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  1. Verilog-Projects Verilog-Projects Public

    FPGA Projects

    Tcl

  2. HDLBits-Solutions HDLBits-Solutions Public

    HDL Bits Solutions

    Verilog

  3. RISC-V-Instruction-Set-Architecture RISC-V-Instruction-Set-Architecture Public

    RISC-V Instruction Set Architecture

    Verilog

  4. shreegw.github.io shreegw.github.io Public

    CSS

  5. PCB-Design PCB-Design Public

    PCB Design Projects