Digital VLSI Testing and Testability

ISCAS-85 Netlist is parsed and a dictionary is generated. The following tasks have been performed:

Timing Models

Simulating circuit for various timing models specified:

1. Transport delay
2. Multiple delay
3. Min-Max delay

Fault Modelling and Simulation

1. Forming a list of all faults.
2. Obtaining collapsed faults using equivalence and dominant fault collapsing.
3. Parallel and Deductive Fault Simulation.
4. SCOAP Controllability and Observability.

Roth's D-Algorithm

Test Vectors generated for a combinational circuit. Supports only two-input gates.