Initial ecc llc integration #125
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* Bender.yml: Update dependencies * axi_vga: Bump version to include an essential performance update * Bender.yml: Switch to released version * doc: Add new parameters, fix typo --------- Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
Fix a typo in the `reg_rsp_t` parameter. This is not very critical as it isn't used, but perhaps it can prevent future headache. Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* target/sim: Add JTAG tasks to read/write 32b registers * target/sim: Add JTAG task to halt and load binary Can be used by platforms to halt CVA6 and preload a shared memory when execution happens on domains different than Cheshire. * target/sim: Clean up added tasks --------- Co-authored-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
…ubber uncorrectable error to cheshire
…ased to the master branch
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