Processor-Design

In this repository, it is presented the whole design of RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verfication of every single block is provided. Although this project has an intermediate to advanced complexity, the main goal of making this repository public is to attract hardware designers to work on project that really matter, instead of spending time and computing resources in merely simulations divorced from reality.

We are periodically documenting every file in order to provide a better understanding about the functionality of each block. In case some questions arise during the exploration of the source code, please do no hesitate to contact us.

Processor-Design

This directory presents the design of a ZDMI Microcontroller Core (ZMC), which is designed to be integrated into a System on Chip (SoC) and it is oriented for calibration applications. The main characteristics of the ZMC are:

RISC architecture: most instructions are executed in only one clock cycle. Additionally, it supports 16 and 32-bits instruction formats.
Built-in PRAM: integrated program memory.
Register file with segmentation of up to 128 data words.
High speed bus interface for peripheral device and external memory attachment.
Continuous execution of the program memory.
High variety of logic and shift instructions.
Synchronization and interrupt mechanism.

Inside each module will be provided a description of its functionality. The Wishbone specification will not be presented due to the copyrights owned by Cadence, platform in which this project was developed.

DISCLAIMER: I do not own or possess any right of the ZMDI Microcontroller specification. I refrain from making public the contents of the technical file that was provided by the tutors and supervisors of this course. This work has been developed only for academic purposes for the course of Processor Design at the VLSI chair of the Technische Universität Dresden. I do give credit to Marco Stolba Marco.Stolba@tu-dresden.de for the development of some modules presented in this directory.

Name		Name	Last commit message	Last commit date
Latest commit History 25 Commits
.github/workflows		.github/workflows
ctrl_fsm		ctrl_fsm
data_mux_3_1/source/rtl/verilog		data_mux_3_1/source/rtl/verilog
flag_reg/source/rtl/verilog		flag_reg/source/rtl/verilog
mask_cndt/source/rtl/verilog		mask_cndt/source/rtl/verilog
pram/source/rtl/verilog		pram/source/rtl/verilog
pram_adr_cnt		pram_adr_cnt
ram_wb/source/rtl/verilog		ram_wb/source/rtl/verilog
reg_file/source/rtl/verilog		reg_file/source/rtl/verilog
test_ALU_reg		test_ALU_reg
wb_interface/source/rtl/verilog		wb_interface/source/rtl/verilog
zmc_adr_gen		zmc_adr_gen
zmc_alu		zmc_alu
zmc_comp/source/rtl/verilog		zmc_comp/source/rtl/verilog
zmc_ctrl/source/rtl/verilog		zmc_ctrl/source/rtl/verilog
zmc_top		zmc_top
CONTRIBUTORS		CONTRIBUTORS
LICENSE		LICENSE
README.md		README.md

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