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Here is a list of other open source processors or simulators that are focused on parallel processing.
- Status: Active
- Language: System Verilog
- Instruction Set: RISC-V
- License: BSD 3-Clause
- Synthesizable: Yes (FPGA proven)
"Time Predictable" VLIW, part of the T-Crest project, focused on safety critical, reliable systems.
- Status: Active
- Language: Chisel
- Instruction Set: Custom (has an LLVM compiler port)
- License: BSD 2-Clause
- Synthesizable: Yes (FPGA proven)
RISC-V based manycore SoC, collaboration between several universities.
- Status: Active
- Language: Verilog
- Instruction Set: RISC-V
- License: Solderpad Hardware License (Apache based)
- Synthesizable: Yes (ASIC proven)
This appears to be a subproject/based on OpenCelerity. From University of Washington.
- Status: Active
- Language: Verilog
- Instruction Set: RISC-V
- License: Solderpad Hardware License (Apache based)
- Synthesizable: Yes (ASIC proven)
Multithreaded SIMT processor written in CHDL, a C++ library by the same author that outputs Verilog. Designed for use with 3D stacked DRAM.
- Status: Low activity
- Language: CHDL
- Instruction Set: Custom
- License: BSD
- Synthesizable: probably? (language compiles to Verilog, but no mention of running this on FPGA)
GPGPU processor from team at University of Madison-Wisconsin.
- Status: Low activity
- Language: Verilog
- Instruction Set: AMD Southern Islands
- License: BSD
- Synthesizable: Yes (FPGA proven)
Manycore processor from team at Princeton. Core is based on OpenSPARC T1, but this replaces the crossbar switch and shared L2 cache of the former with a scalable 2D mesh network-on-chip.
- Status: Active
- Language: Verilog
- Instruction Set: SPARC
- License: GPLv2
- Synthesizable: Yes (ASIC proven)
Tiled multicore SoC component library from Munich Technical University (Technische Universität München (TUM)). The modular design allows combining other IP libraries and processor cores.
- Status: Active
- Language: Verilog
- Instruction Set: multiple, currently OpenRISC.
- License: MIT
- Synthesizable: Yes
Cycle-accurate compute core simulator based on NVidia architecture by team at University of British Columbia. Executes NVidia PTX intermediate code.
- Status: Last change was 2 years ago
- Language: C++
- Instruction Set: NVidia PTX
- License: BSD
- Synthesizable: No
Synthesizable General-Purpose SIMT Processor. Supports hardware multithreading. Uses RISC-V (32I) instruction set.
- Status: Inactive (?)
- Language: VHDL
- Instruction Set: RISC-V 32i (integer only)
- License: None
- Synthesizable: Yes (FPGA proven)
Manycore processor based on SecretBlaze core.
- Status: ?
- Language: VHDL
- Instruction Set: Microblaze
- License: GPLv3
- Synthesizable: yes (FPGA proven)
Simulator and Verilog compute core with a custom instruction set.
- Status: Inactive, incomplete
- Language: Verilog
- Instruction Set: Custom
- License: ?
- Synthesizable: Yes