Issues: intel/rohd
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Add New feature or request
selectIndex
directly to LogicArray
(and Logic
?) to enable one-liner accesses in generated SV.
enhancement
#484
opened Apr 29, 2024 by
mkorbel1
Make full array assignments compressed to 1 line (or in-lined) in generated SystemVerilog
enhancement
New feature or request
#482
opened Apr 15, 2024 by
mkorbel1
Add better tests for simulator phasing
enhancement
New feature or request
#479
opened Apr 2, 2024 by
mkorbel1
LogicArray
ports on Interface
s are not uniquified by uniquify
in connectIO
bug
#477
opened Mar 25, 2024 by
mkorbel1
PairInterface
does not accept LogicArray
s (or anything besides Port
)
bug
#476
opened Mar 25, 2024 by
mkorbel1
Static analysis for combinational loops
enhancement
New feature or request
#469
opened Feb 28, 2024 by
mkorbel1
Refractor Riverpod state management to Bloc state management
enhancement
New feature or request
flutter
Changes are related to Flutter code (e.g. Debug UI)
#466
opened Feb 26, 2024 by
quekyj
Trace for driver of a signal
enhancement
New feature or request
flutter
Changes are related to Flutter code (e.g. Debug UI)
#465
opened Feb 26, 2024 by
quekyj
Signal to code navigation
enhancement
New feature or request
flutter
Changes are related to Flutter code (e.g. Debug UI)
#464
opened Feb 26, 2024 by
quekyj
Hierarchy Viewer need to click refresh button and then click on the signal to refresh the value
bug
Something isn't working
enhancement
New feature or request
flutter
Changes are related to Flutter code (e.g. Debug UI)
good first issue
Good for newcomers
#462
opened Feb 22, 2024 by
quekyj
Add a way to run the Simulator "until" a certain time (without ending the simulation)
enhancement
New feature or request
good first issue
Good for newcomers
#451
opened Jan 2, 2024 by
mkorbel1
Add a utility for "waiting" a certain amount of time in the Simulator.
enhancement
New feature or request
good first issue
Good for newcomers
#450
opened Jan 2, 2024 by
mkorbel1
Simulation Bug: WaveDumper Function Must Be Placed Before Simulator Class to Prevent Errors
bug
Something isn't working
#446
opened Dec 13, 2023 by
quekyj
Improve lint avoidance for width expansion
enhancement
New feature or request
#444
opened Dec 11, 2023 by
mkorbel1
Allow New feature or request
SynthBuilder
to accept multiple Module
s.
enhancement
#434
opened Nov 6, 2023 by
mkorbel1
PairInterface
should enable receiving/driving all sub-interfaces as well
enhancement
#433
opened Nov 6, 2023 by
mkorbel1
Add capability to New feature or request
PairInterface
to modify naming at time of addSubInterface
enhancement
#432
opened Nov 6, 2023 by
mkorbel1
Add a quick way to instantiate simple external SystemVerilog modules.
enhancement
New feature or request
#431
opened Nov 5, 2023 by
mkorbel1
Improve documentation on instantiating SystemVerilog modules
documentation
Improvements or additions to documentation
#430
opened Nov 5, 2023 by
mkorbel1
Avoid module creation for simple constant scenarios in gates
enhancement
New feature or request
#429
opened Nov 3, 2023 by
mkorbel1
Simulator optimization: don't simulate signals that don't matter (optionally)
enhancement
New feature or request
#428
opened Nov 3, 2023 by
mkorbel1
Add capabilities to transpose New feature or request
LogicArray
s
enhancement
#427
opened Nov 1, 2023 by
mkorbel1
Add example on how to use Logic Array assignment would be good
documentation
Improvements or additions to documentation
enhancement
New feature or request
#426
opened Oct 27, 2023 by
quekyj
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