Discussions

• 3 You must be logged in to vote

  💡

  ROHD Dev Tools Extension Proposal

  quekyj started Sep 25, 2023 in Ideas

  

  

  

  

  2
• 3 You must be logged in to vote

  💬

  equivalent of systemC wait( time ) or SystemVerilog #time

  AdamRose66 started Jan 2, 2024 in General

  

  

  5
• 2 You must be logged in to vote

  🙏

  Elements

  eulere28 asked Oct 27, 2023 in Q&A · Unanswered

  

  

  1
• 1 You must be logged in to vote

  💡

  Enhanced interactive ROHD simulation debug

  mkorbel1 started May 12, 2022 in Ideas

  

  

  2
• 1 You must be logged in to vote

  💬

  New tagging

  quekyj started Aug 11, 2023 in General

  

  

  1
• 2 You must be logged in to vote

  💡

  ROHD Framework Language Server Model

  quekyj started Jul 17, 2023 in Ideas

  

  

  0
• 1 You must be logged in to vote

  🙏

  How to use withset in Conditionals

  quekyj asked May 16, 2023 in Q&A · Closed · Unanswered

  

  

  1
• 1 You must be logged in to vote

  🙏

  How to use blocking and non-blocking in System Verilog always_ff

  quekyj asked May 18, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Check output changes based on the inputs changes, System Verilog assert property

  quekyj asked May 18, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  clock control, when to start and stop and reset

  quekyj asked May 18, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Synchronous Reset

  quekyj asked May 18, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Triple equals === in ROHD

  quekyj asked May 2, 2023 in Q&A · Closed · Answered

  

  

  1
• 1 You must be logged in to vote

  🙏

  When to use Simulator.injectAction vs Simulator.registerAction?

  quekyj asked Apr 11, 2023 in Q&A · Unanswered

  

  

  1
• 1 You must be logged in to vote

  🙏

  Misuse of Simulator not throwing informative exception message

  quekyj asked Apr 11, 2023 in Q&A · Unanswered

  

  

  1
• 1 You must be logged in to vote

  🙏

  Does conditional take bracket for grouping?

  quekyj asked May 2, 2023 in Q&A · Unanswered

  

  

  0
• 1 You must be logged in to vote

  🙏

  Inconsistent shift left and right operator

  quekyj asked May 2, 2023 in Q&A · Unanswered

  

  

  0
• 2 You must be logged in to vote

  🙏

  The Const() in ROHD require explicit width declaration

  quekyj asked Mar 29, 2023 in Q&A · Unanswered

  

  

  

  

  2
• 2 You must be logged in to vote

  🙏

  Rule of Thumb / best practices for ROHD class and function

  quekyj asked Mar 27, 2023 in Q&A · Closed · Answered

  

  

  2
• 1 You must be logged in to vote

  🙏

  ROHD Unit Testing Validation in Sequential

  quekyj asked Mar 27, 2023 in Q&A · Answered

  

  

  

  

  3
• 2 You must be logged in to vote

  🙏

  Inject vs Put

  quekyj asked Mar 22, 2023 in Q&A · Unanswered

  

  

  1
• 1 You must be logged in to vote

  🙏

  Printing of useful information when unit test fail

  quekyj asked Mar 20, 2023 in Q&A · Closed · Answered

  

  

  2
• 1 You must be logged in to vote

  🙏

  ROHD withset multiple bits at once

  quekyj asked Mar 13, 2023 in Q&A · Answered

  

  

  

  

  5
• 1 You must be logged in to vote

  🙏

  ROHD Blocking and Non-Blocking Assignment

  quekyj asked Mar 13, 2023 in Q&A · Answered

  

  

  2
• 1 You must be logged in to vote

  🙏

  ROHD swizzle output variable must be equal to the swizzle result width

  quekyj asked Mar 13, 2023 in Q&A · Closed · Answered

  

  

  

  

  8
• 2 You must be logged in to vote

  🙏

  About Simulator

  chykon asked Feb 27, 2023 in Q&A · Answered

  

  

  3