Add Verilog macro helpers to reduce duplication #92
Triggered via pull request
April 14, 2024 21:52
Status
Success
Total duration
4h 49m 52s
Artifacts
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firesim-non-aws-run-tests.yml
on: pull_request
filter-jobs-on-changes
4s
cancel-prior-workflows
2s
documentation-check
1m 7s
cpp-lint
1m 54s
check-conda-lock-modified
0s
run-xilinx_alveo_u250-check-docs-generated-components
11s
run-parallel-vcs-metasims-and-xilinx_alveo_u250-driver
15m 57s
run-basic-linux-poweroffs-xilinx_alveo_u250
0s
run-local-fpga-buildbitstream
3h 39m
cleanup-local-fpga-repo
11s