Add Verilog macro helpers to reduce duplication

[abejgonzalez]

Use Verilog macros to instantiate wires/ports/etc in the Verilog sections of FireSim.

TL;DR: Writing Verilog without bundle connects is hard. Instead, I made AXI macros for it! Now Verilog is easy!

Related PRs / Issues

UI / API Impact

Verilog / AGFI Compatibility

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• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
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• Did you specify the Verilog / AGFI compatibility impact?

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[abejgonzalez]

TODO: Change to be based on main on #1671 is done.

[abejgonzalez]

@Mergifyio rebase main

[mergify]

rebase main

✅ Branch has been successfully rebased

[joonho3020]

Great stuff.
I would prefer defining all the macros in a single fpga_top_macros.vh file, but this seems fine as well.