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RocketChip v1.6

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@michael-etzkorn michael-etzkorn released this 10 Oct 12:40
v1.6
44b0b82
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Learn about vigilant mode.

Version 1.6.0

Added

  • Support for Chisel 3.5.3 (#2931, #2937, #2947, #3005)
  • Support for Scala 2.12.15 (#2947)
  • Properly-sized don't cares for FPU typeTag fields (#2949)
  • Add a virtual argument to TLBEntry.sectorHit function (#2952)
  • Support building PTW with no PTECache (#2962)
  • Update IncoherentBusTopology to support multiclock and custom clocking (#2940)
  • Allow forcing RocketTiles into separate PRCI groups (#2842)
  • Add a WithHypervisor config (#2946)
  • Add ScalaDoc documentation for I$ (#3001)

Changed

  • AHPParameters and APBParameters:
    • PROT_PRIVILEDGED - This was a typo. It is now PROT_PRIVILEGED. (#2925)
  • GrountTestTile: use generic BuildHellaCache key (#2919)
  • copy EICG wrapper from vsrc when using Clock Gate Model (#2969)
  • PTW page fault instead of access exception if PTE reserved bit set (#2913, #2934)
    • PTE_RSVD was introduced into Spike in riscv-software-src/riscv-isa-sim#750
    • Reserved PTE bits report page fault instead of access exception.
    • Add an additional bit pf to PTWResp and TLBEntryData to pipe this through.
  • Have HFENCE.GVME sfence.bits.hg=1, hv=0 only target TLB entries with V=1 (and not V=0) (#2954)
  • Update Instructions from riscv-opcodes and separate out rocket-specific custom instructions (#2956, #2972)
  • Decode: switch to using Chisel Decode API (#2836, #2994)
  • Convert toaxe.py to python3 (#3034)
  • make AsyncClockGroupsKey a node generator (#2935)
  • change debug module name to tlDM (#3029)
  • As part of a larger migration begin refactoring files to chisel3:

Fixed

  • Proper translation to HRProt3 in AHB Protocol (#2928)
  • Assert HasFSDirty false (#2997)
  • VSStatus is now read-only and dirty when RoCC is enabled (#2984)
  • RocketCore: avoid false RAW/WAW hazards for integer instructions using an x register whose numeric specifier coincides with a previous instruction's f register. (#2945)
  • Correct rocc_illegal to use reg_vsstatus.xs field (#2983)
  • Zero out aux_pte.reserved_for_future whenever ``aux_pte.ppn` is driven (#3003)
  • Prevent ILTB miss fault PTW thrashing D$ (#3004)
  • Prevent nonsensical use of RVE with Hypervisor (#2988)
  • Explicity outline Rocket's lack of support for haveFSDirty (#2997)
  • Fix bit-width out of range issue when both Sv57 and Hypervisor are enabled (#3006)
  • Fix synthesizability of RoccBlackBox with Vivado (#3035)

Removed

  • Remove Object Model from Diplomacy (#2967)
  • Removed RegEnable explicit arguments in preparation for changes in Chisel 3.6 (#2986)
  • Removed all mentions of Travis CI and .travis.yml file (#2647)
  • Remove TraceGen from `HeterogeneousTileExampleConfig (#2923)
Assets 2