[TestDriver.v] Set initial clock = 1'b1;

[Waxpple]

Related issue: Potential timing violation in the initial condition.

Type of change: other enhancement

Impact: no functional change

Development Phase: implementation

Release Notes

Set clock = 1'b1; to avoid the first reset signal only using half of the clock cycle.
If want to avoid the first reset cycle using only half clock period causing timing violation, modify TestDriver.v like this:

The waveform will be:

The original testbench will look like this:

The waveform will be

[linux-foundation-easycla]

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• ✅ login: Waxpple / name: Waxpple (cde5a3b)

[jerryz123]

What timing violation are you seeing? Are you assuming sync or async reset?

[Waxpple]

What timing violation are you seeing? Are you assuming sync or async reset?

Sorry for the late reply.

Setup time violation like this:

I assume the reset signal is synchronized.
However, It will reset for a couple of cycles, so the actual timing violation is not critical.
But if the initial condition is set as above, it is not easy to trigger the timing check and makes it easier to debug the timing violation if there is any.