Merge pull request #3626 from chipsalliance/width-fix

Fix extraction-width warnings

src/main/scala/devices/debug/Debug.scala

@@ -922,7 +922,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     // Outer.hamask doesn't consider the hart selected by dmcontrol.hartsello,
     // so append it here
     when (selectedHartReg < nComponents.U) {
-      hamaskFull(selectedHartReg) := true.B
+      hamaskFull(if (nComponents == 1) 0.U(0.W) else selectedHartReg) := true.B
     }
 
     io.innerCtrl.ready := true.B
@@ -1046,7 +1046,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
           }
         }
       }
-      DMCS2RdData.haltgroup := hgParticipateHart(selectedHartReg)
+      DMCS2RdData.haltgroup := hgParticipateHart(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
 
       if (nExtTriggers > 0) {
         val hgSelect = Reg(Bool())
@@ -1730,7 +1730,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     // This is not an initialization!
     val ctrlStateReg = Reg(chiselTypeOf(CtrlState(Waiting)))
 
-    val hartHalted   = haltedBitRegs(selectedHartReg)
+    val hartHalted   = haltedBitRegs(if (nComponents == 1) 0.U(0.W) else selectedHartReg)
     val ctrlStateNxt = WireInit(ctrlStateReg)
 
     //------------------------

src/main/scala/devices/debug/SBA.scala

@@ -307,7 +307,7 @@ class SBToTL(implicit p: Parameters) extends LazyModule {
     val counter = RegInit(0.U((log2Ceil(cfg.maxSupportedSBAccess/8)+1).W))
     val vecData   = Wire(Vec(cfg.maxSupportedSBAccess/8, UInt(8.W)))
     vecData.zipWithIndex.map { case (vd, i) => vd := io.dataIn(8*i+7,8*i) }
-    muxedData := vecData(counter)
+    muxedData := vecData(counter(log2Ceil(vecData.size)-1,0))
 
     // Need an additional check to determine if address is safe for Get/Put
     val rdLegal_addr = edge.manager.supportsGetSafe(io.addrIn, io.sizeIn, Some(TransferSizes(1,cfg.maxSupportedSBAccess/8)))

src/main/scala/devices/tilelink/Error.scala

@@ -60,7 +60,7 @@ class TLError(params: DevNullParams, buffer: Boolean = true, beatBytes: Int = 4)
 
       // ReleaseAck is not allowed to report failure
       dc.bits.opcode  := ReleaseAck
-      dc.bits.param   := VecInit(toB, toN, toN)(c.bits.param)
+      dc.bits.param   := VecInit(toB, toN, toN)(c.bits.param(1,0))
       dc.bits.size    := c.bits.size
       dc.bits.source  := c.bits.source
       dc.bits.sink    := 0.U

src/main/scala/rocket/CSR.scala

@@ -957,15 +957,16 @@ class CSRFile(
     Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),
     Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))
   val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)
+  val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)
   val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U
   val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U
   val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
   val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
   val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))
   val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))
   val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)
-  val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_lsbs), read_medeleg(cause_lsbs))
-  val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_lsbs), read_hedeleg(cause_lsbs))
+  val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))
+  val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))
   def mtvecBaseAlign = 2
   def mtvecInterruptAlign = {
     require(reg_mip.getWidth <= xLen)

src/main/scala/rocket/ICache.scala

@@ -504,7 +504,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
         // @todo Accessing ITIM correspond address will be able to read cacheline?
         //       is this desired behavior?
         addrInScratchpad(io.s1_paddr) && scratchpadWay(io.s1_paddr) === i.U)
-    val s1_vb = vb_array(Cat(i.U, s1_idx)) && !s1_slaveValid
+    val s1_vb = vb_array(Cat(i.U, s1_idx).pad(log2Ceil(nSets*nWays))) && !s1_slaveValid
     val enc_tag = tECC.decode(tag_rdata(i))
     /** [[tl_error]] ECC error bit.
       * [[tag]] of [[tag_array]] access.

src/main/scala/tilelink/Monitor.scala

@@ -611,7 +611,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec
     val log_a_size_bus_size   = log2Ceil(a_size_bus_size)
     def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
 
-    val inflight = RegInit(0.U(edge.client.endSourceId.W))
+    val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
     inflight.suggestName("inflight")
     val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
     inflight_opcodes.suggestName("inflight_opcodes")
@@ -632,7 +632,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec
     val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
     a_sizes_set.suggestName("a_sizes_set")
 
-    val a_opcode_lookup = WireInit(0.U((1 << log_a_opcode_bus_size).W))
+    val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
     a_opcode_lookup.suggestName("a_opcode_lookup")
     a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
 
@@ -723,7 +723,7 @@ class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirec
     val log_c_size_bus_size   = log2Ceil(c_size_bus_size)
     def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
 
-    val inflight         = RegInit(0.U(edge.client.endSourceId.W))
+    val inflight         = RegInit(0.U((2 max edge.client.endSourceId).W))
     val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
     val inflight_sizes   = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
     inflight.suggestName("inflight")

src/main/scala/tilelink/WidthWidget.scala

@@ -177,14 +177,19 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
       // The assumption is that this sort of situation happens only where
       // you connect a narrow master to the system bus, so there are few sources.
 
-      def sourceMap(source: UInt) = {
+      def sourceMap(source_bits: UInt) = {
+        val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
         require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
         val keepBits = log2Ceil(edgeOut.manager.beatBytes)
         val dropBits = log2Ceil(edgeIn.manager.beatBytes)
         val sources  = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
         val a_sel = in.a.bits.address(keepBits-1, dropBits)
         when (in.a.fire) {
-          sources(in.a.bits.source) := a_sel
+          if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
+            sources(0) := a_sel
+          } else {
+            sources(in.a.bits.source) := a_sel
+          }
         }
 
         // depopulate unused source registers: