Design-and-ASIC-Implementation-of-UART

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

UART stands for universal asynchronous receiver / transmitter and defines a protocol, or set of rules, for exchanging serial data between two devices. UART is very simple and only uses two wires between transmitter and receiver to transmit and receive in both directions. so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in VCS, synthesized in Design Compiler, and extracted in ICC II in SAED 32 nm CMOS cell library.

Introduction

The first step of the ASIC Design flow is the register transfer level (RTL) design, where the high-level architectural description is transformed into a digital representation using VerilogL. This involves designing and implementing the behavior and connections of individual digital components.

UART can be divided into sending module and receiving module according to functions. It is worth noting that in order to take into account the accuracy and efficiency of information transmission, the sending module and the receiving module have different methods of confirming information.

During the transmission, the transmitter transmits the parallel data by converting it into a serial data stream and includes „start bit‟ and „stop bit‟

During the receiving operation, the receiver receives the serial bit data stream and converts it into parallel data by rejecting the „start bit‟ and „stop bit‟

UART Data Frame

UART frame contain start and stop bits, and optional parity bit.

• Start bit: Because UART is asynchronous, the transmitter needs to signal that data bits are coming. This is accomplished by using the start bit. The start bit is a transition from the idle high state to a low state, and immediately followed by user data bits.
• Stop bit: After the data bits are finished, the stop bit indicates the end of user data. The stop bit is a transition back to the high state.
• Data bits: The data bits are the user data or “useful” bits and come immediately after the start bit. 7 or 8 bits is most common. These data bits are usually transmitted with the least significant bit first.
• Parity bit: A UART frame can also contain an optional parity bit that can be used for error detection. The value of the parity bit depends on the type of parity being used (even or odd)

Timing and Synchronization

It is possible for a phase delay to occur during the frame's passage through the system until it reaches the UART_RX, so we will need to use higher clock frequency to oversampling the data.UART_RX support oversampling by 8, 16, 32. data_sampling block in UART_RX will take 3 samples in the middle of clock period to ensure sampl the correct value.

For example: Oversampling by 8 means that the clock speed of UART_RX is 8 times the speed of UART_TX

UART clock

the transmitter and receiver do not share a common clock signal. in this repository I used two clock UART_CLK_TX for transmitter module and UART_CLK_RX for receiver module and used the baud rate 115200 and prescale (division factor) = 32 :

baud rate = 115200 bits/sec = 112.5 KHz

UART_CLK_TX = 112.5 KHz

UART_CLK_RX =115200 * 32 = 3.515 MHz

Simulation using VCS

UART_RX simulation

UART_TX simulation

Synthesized View of UART chip (post DFT)

Synthesized view of UART connections (post DFT)

Powerplanning layout

Placement layout

turn off visibility of the P/G mesh to better see the placement

Clock Tree

Scan Chain

Routing layout

IR drop

to do analyze_power_plan I use set_virtual_pad at nets VDD and VSS

Congestion map

Contributing

Contributions to this project are welcome. If you find any issues or have suggestions for improvements, please feel free to submit a pull request or open an issue in the repository.