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basemhesham/README.md

Hi 👋, I'm Basem Hesham

Physical Design Engineer

I am an extremely motivated Physical Design Engineer with interests in the field of Digital IC Design and Computer Architecture.

As a dedicated and hardworking individual, I am always seeking to learn and grow both personally and professionally. I am excited to connect with like-minded individuals in the field and explore opportunities to contribute to the industry's growth and development.

My area of interest lies in ASIC design, Timing analysis(STA), Physical Design, and Logic Synthesis.

GIF

  • 🔭 I am currently senior student at Zagzig University studying Communication and Electronics Engineering.

  • 🌱 I’m currently learning physical verification , Floor planning , Power planning , Placement , Routing and chip finishing.

  • 💬 Ask me about FPGA/ASIC Design Design "Verilog, STA, PnR"

  • 📫 How to reach me basemhesham159@gmail.com

  • 📄 Know about my experiences Resume




Connect with me 🤝

Popular repositories

  1. Design-and-ASIC-Implementation-of-UART Design-and-ASIC-Implementation-of-UART Public

    This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been s…

    Verilog 6 3

  2. Digital-Design-of-FIR-Filter-Transposed-Structure Digital-Design-of-FIR-Filter-Transposed-Structure Public

    Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.

    Verilog 1

  3. basemhesham basemhesham Public

  4. Verilog_HDL Verilog_HDL Public

    Verilog

  5. 32-bit_single_cycle_MIPS_processor 32-bit_single_cycle_MIPS_processor Public

    Verilog