VSD-IAT: Static Timing Analysis - Basics to Advanced

STA stands for Static Timing Analysis. It is a method to verify the timing correctness of a chip. It evaluates the delays of each timing path in a digital circuit incurred when a signal propagates through it. By this delay calculation, it is able to determine whether the chip meets or violates the timing constraints. In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.

Table of contents

• Abstract
• Day-1 Lab
• Day-2 Lab
• Day-3 Lab
• Day-4 Lab
• Day-5 Lab
• Acknowledgement
• Author

Abstract

In this 5 days workshop we have used open-source sign-off timing analysis tool STA and open-source Sky130 libraries, to perform the day-wise labs. Each day has a specific set of task to be completed under this workshop. Following is the detailed proof of work of labs of each day.

🔲 Day-1 Lab

[Objective]: To understand the inputs to openSTA and run script commands.

[1.] Verilog netlist simple.v (Input to openSTA)

[2.] Library sky130_fd_sc_hd_tt_025C_1v80.lib file (Input to openSTA)

[3.] SDC constraint simple.sdc file (Input to openSTA)

[4.] openSTA run script results

🔲 Day-2 Lab

[Objective]: To understand liberty files, SPEF, timing reports.

[1.] Following are all the cells present in simple_max.lib

[2.] Number of pins in cell NAND2_X1 in simple_max.lib

    pin 'o'
    pin 'a'
    pin 'b'  

[3.] Difference between NAND2_X1 and NAND3_X1

I have observed the following differences between the two.

• First is the number of input pins both have.

• Second is the difference in maximum output capacitance.
  

• Third is the difference of the transition times and delays.

[4.] Difference between ‘simple_max.lib’ and ‘simple_min.lib’

The main difference that I was able to find was in the delays as shown below.

🔲 Day-3 Lab

We are performing timing analysis for the circuit shown below.

[1.] Command : report_checks -from F1/CK

🔲 Day-4 Lab

[1.] Clock Gating Checks

run.tcl file

runscript

[2.] Async Pin Checks

run.tcl file

runscript

🔲 Day-5 Lab

(Eco Insertion part) run.tcl file

runscript

s27.v file

s27_eco.v file

Acknowledgement

• Kunal Ghosh, Co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd.
• Vikas Sachdeva, Advisor, Tech and VLSI Coach, Trainer and Innovator at vlsideepdive.

Author

Arpit Sharma, B.Tech (2019-23), IPEC, Sahibabad, Delhi-NCR, India
Contact: arpitniraliya306@gmail.com, 1900300310018@ipec.org.in