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GTKWave.png

GTKWave.png

 
 

LICENSE

LICENSE

 
 

README.md

README.md

 
 

Reference_Circuit.png

Reference_Circuit.png

 
 

Sklansky.v

Sklansky.v

 
 

Sklansky.vcd

Sklansky.vcd

 
 

Sklansky_tb.v

Sklansky_tb.v

 
 

blackcells.v

blackcells.v

 
 

gp.v

gp.v

 
 

greycells.v

greycells.v

 
 

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About

16-bit Slansky Adder design using verilog HDL

Reference Circuit

Screenshot 2021-05-14 at 17 36 36

Output

  • Test Bench

TestBenchOutput

  • GTK Waveform

GTKWave

About

16-bit Slansky Adder design using verilog HDL

Topics

verilog gtkwave vlsi testbench iverilog sklansky-adder

Resources

Readme

License

MIT license
Activity

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