This release contains:

- A bigger and improved documentation including command line tools and the Python infrastructure
- ModelSim support
- UVVM integration
- Continuous Integration on AppVeyor
- Improved cache IP cores and better ocram simulation models
- Improved testbenches: e.g. sorting networks tested with OSVVMs scoreboard.

.appveyor.yml

@@ -0,0 +1,36 @@
+version: 1.1.0-b{build}
+clone_folder: c:\projects\poc
+init:
+  # Checking that DEP is enabled
+  - ps: Write-Host "Initializing virtual machine ..."
+  - ps: git --version
+  - ps: $env:Path = $env:Path.Replace("Python27", "Python35-x64")
+
+install:
+  - ps: Write-Host "Installing requirements..."
+  - ps: python --version
+  - ps: python -m pip install pip --upgrade
+  - ps: python -m pip install -r .\requirements.txt
+  - ps: python -m pip list --format=columns
+  - ps: Write-Host "Configuring PoC..."
+  - ps: cp .\tools\AppVeyor\config.private.ini .\py\
+  - ps: cp .\tools\AppVeyor\my_project.vhdl .\tb\common\
+  - ps: .\poc.ps1
+
+build: off
+
+build_script:
+  - ps: Write-Host "Testing query interface..."
+  - ps: .\poc.ps1 query INSTALL.PoC:InstallationDirectory
+  - ps: Write-Host "Testing information interface..."
+  - ps: .\poc.ps1 list-testbench PoC.*
+  - ps: .\poc.ps1 list-netlist PoC.*
+  - ps: Write-Host "Testing simulators..."
+  - ps: .\poc.ps1 --dryrun ghdl PoC.arith.prng --analyze --elaborate
+  - ps: Write-Host "Testing synthesizers..."
+#  - ps: .\poc.ps1 --dryrun quartus PoC.arith.prng --board=DE4
+#  - ps: .\poc.ps1 --dryrun lse PoC.arith.prng --board=ECP5Versa
+#  - ps: .\poc.ps1 --dryrun xst PoC.arith.prng --board=KC705
+#  - ps: .\poc.ps1 --dryrun vivado PoC.arith.prng --board=KC705
+#  - ps: Write-Host "Testing core generators..."
+#  - ps: .\poc.ps1 --dryrun coregen PoC.xil.mig.Atlys_1x128 --board=Atlys

.gitignore

@@ -9,7 +9,13 @@
 __pycache__
 
 # ignore build directories
-docs/_build/
+/docs/_build/
+/docs/PyInfrastructure/*
+!/docs/PyInfrastructure/.gitempty
+!/docs/PyInfrastructure/.publish
+!/docs/PyInfrastructure/README.md
+!/docs/PyInfrastructure/index.rst
+
 
 # ignore files in netlist/
 /netlist/
@@ -94,3 +100,4 @@ other/diamond/.spreadsheet_view.ini
 !.git*
 !.publish
 !README.md
+other/PrecisionRTL/

.gitmodules

@@ -10,3 +10,6 @@
 [submodule "docs/_themes/sphinx_rtd_theme"]
 	path = docs/_themes/sphinx_rtd_theme
 	url = https://github.com/VLSI-EDA/sphinx_rtd_theme.git
+[submodule "lib/uvvm"]
+	path = lib/uvvm
+	url = https://github.com/VLSI-EDA/UVVM_All.git

.landscape.yml

@@ -30,6 +30,7 @@ ignore-paths:
 - sim
 - src
 # - tb
+- tcl
 - temp
 # - tools
 - ucf

.readthedocs.yml

@@ -0,0 +1,5 @@
+#formats:
+#  - pdf
+requirements_file: tools/ReadTheDocs/requirements.txt
+python:
+  version: 3

README.md

@@ -3,7 +3,9 @@
 
 [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/master/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/master)
 [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=master)](https://travis-ci.org/VLSI-EDA/PoC/branches)
+[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/master?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/master)
 [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest)
+[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=master)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=master)
 [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC)
 ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
 [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
@@ -85,15 +87,18 @@ Windows. See [Requirements][211] for further details.
     A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
  -  [OS-VVM][2132]  
     Open Source VHDL Verification Methodology.
- -  [VUnit][2133]  
+ -  [UVVM][2133]  
+    Universal VHDL Verification Methodology.
+ -  [VUnit][2134]  
     An unit testing framework for VHDL.
 
 All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the
 [`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries.
 
 [2131]: https://github.com/potentialventures/cocotb
 [2132]: https://github.com/JimLewis/OSVVM
-[2133]: https://github.com/VUnit/vunit
+[2133]: https://github.com/UVVM/UVVM_All
+[2134]: https://github.com/VUnit/vunit
 
 [201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html
 [202]: http://poc-library.readthedocs.io/
@@ -103,7 +108,7 @@ All dependencies are available as GitHub repositories and are linked to PoC as G
 
 ### 2.2 Download
 
-The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone`
+The PoC-Library can be downloaded as a [zip-file][221] (latest 'master' branch), cloned with `git clone`
 or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See
 the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`.
 

README.tpl

@@ -3,12 +3,15 @@
 
 [![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@}/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/{@BRANCH@})
 [![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch={@BRANCH@})](https://travis-ci.org/VLSI-EDA/PoC/branches)
+[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/{@BRANCH@}?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/{@BRANCH@})
 [![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest)
+[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch={@BRANCH@})](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch={@BRANCH@})
 [![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC)
 ![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)
 [![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)
 [![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md)
 
+
 This library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - 
 Faculty of Computer Science, Technische Universität Dresden, Germany 
 **http://vlsi-eda.inf.tu-dresden.de**
@@ -48,8 +51,8 @@ infrastructure to offer a command line based frontend.
 
 ## 2 Quick Start Guide
 
-This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in the
-[Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples.
+This **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in
+the [Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples.
 
 
 ### 2.1 Requirements and Dependencies
@@ -84,15 +87,18 @@ Windows. See [Requirements][211] for further details.
     A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
  -  [OS-VVM][2132]  
     Open Source VHDL Verification Methodology.
- -  [VUnit][2133]  
+ -  [UVVM][2133]  
+    Universal VHDL Verification Methodology.
+ -  [VUnit][2134]  
     An unit testing framework for VHDL.
 
 All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the
 [`PoCRoot\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries.
 
 [2131]: https://github.com/potentialventures/cocotb
 [2132]: https://github.com/JimLewis/OSVVM
-[2133]: https://github.com/VUnit/vunit
+[2133]: https://github.com/UVVM/UVVM_All
+[2134]: https://github.com/VUnit/vunit
 
 [201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html
 [202]: http://poc-library.readthedocs.io/
@@ -102,7 +108,7 @@ All dependencies are available as GitHub repositories and are linked to PoC as G
 
 ### 2.2 Download
 
-The PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone`
+The PoC-Library can be downloaded as a [zip-file][221] (latest '{@BRANCH@}' branch), cloned with `git clone`
 or embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See
 the [Download][222] page for further details. The installation directory is referred to as `PoCRoot`.
 

docs/ChangeLog/2014/index.rst

@@ -0,0 +1,11 @@
+.. _CHANGE:2014:
+
+2014
+####
+
+.. contents:: Content of this page
+   :local:
+
+.. toctree::
+
+   v0.0.0 <v0.0.0>

docs/ChangeLog/2014/v0.0.0.rst

@@ -0,0 +1,6 @@
+.. _CHANGE:v0.0.0:
+
+New in v0.0.0 (16.12.2014)
+================================================================================================================================================================
+
+* Initial commit

docs/ChangeLog/2015/index.rst

@@ -0,0 +1,55 @@
+.. _CHANGE:2015:
+
+2015
+####
+
+.. contents:: Content of this page
+   :local:
+
+.. only:: html
+
+   .. toctree::
+
+      v0.18.0 <v0.18.0>
+      v0.17.0 <v0.17.0>
+      v0.16.0 <v0.16.0>
+      v0.15.0 <v0.15.0>
+      v0.14.0 <v0.14.0>
+      v0.13.0 <v0.13.0>
+      v0.12.0 <v0.12.0>
+      v0.11.0 <v0.11.0>
+      v0.10.0 <v0.10.0>
+      v0.9.0 <v0.9.0>
+      v0.8.0 <v0.8.0>
+      v0.7.0 <v0.7.0>
+      v0.6.0 <v0.6.0>
+      v0.5.0 <v0.5.0>
+      v0.4.0 <v0.4.0>
+      v0.3.0 <v0.3.0>
+      v0.2.0 <v0.2.0>
+      v0.1.0 <v0.1.0>
+
+
+
+.. only:: latex
+
+   .. toctree::
+
+      v0.1.0 <v0.1.0>
+      v0.2.0 <v0.2.0>
+      v0.3.0 <v0.3.0>
+      v0.4.0 <v0.4.0>
+      v0.5.0 <v0.5.0>
+      v0.6.0 <v0.6.0>
+      v0.7.0 <v0.7.0>
+      v0.8.0 <v0.8.0>
+      v0.9.0 <v0.9.0>
+      v0.10.0 <v0.10.0>
+      v0.11.0 <v0.11.0>
+      v0.12.0 <v0.12.0>
+      v0.13.0 <v0.13.0>
+      v0.14.0 <v0.14.0>
+      v0.15.0 <v0.15.0>
+      v0.16.0 <v0.16.0>
+      v0.17.0 <v0.17.0>
+      v0.18.0 <v0.18.0>

docs/ChangeLog/2015/v0.1.0.rst

@@ -0,0 +1,44 @@
+.. :CHANGE:v0.1.0:
+
+New in v0.1.0 (19.02.2015)
+================================================================================================================================================================
+
+* New packages:
+
+  * board - common development board configurations
+  * config - extract configuration parameters from device names
+  * utils - common utility functions
+  * strings - a helper package for string handling
+  * vectors - a helper package for std_logic_vector and std_logic_matrix
+  * arith
+  * fifo
+
+* New modules
+
+  * PoC.arith - arithmetic modules
+
+    * arith_counter_gray
+    * arith_counter_ring
+    * arith_div
+    * arith_prefix_and
+    * arith_prefix_or
+    * arith_prng
+    * arith_scaler
+    * arith_sqrt
+
+  * PoC.fifo - FIFOs
+
+    * fifo_cc_got
+    * fifo_cc_got_tempgot
+    * fifo_cc_got_tempput
+    * fifo_ic_got
+    * fifo_glue
+    * fifo_shift
+
+  * PoC.mem.ocram - On-Chip RAMs
+
+    * ocram_sp
+    * ocram_sdp
+    * ocram_esdp
+    * ocram_tdp
+    * ocram_wb

docs/ChangeLog/2015/v0.10.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.10.0:
+
+New in v0.10.0 (23.07.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.11.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.11.0:
+
+New in v0.11.0 (07.08.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.12.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.12.0:
+
+New in v0.12.0 (25.08.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.13.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.13.0:
+
+New in v0.13.0 (04.09.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.14.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.14.0:
+
+New in v0.14.0 (28.09.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.15.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.15.0:
+
+New in v0.15.0 (13.11.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.16.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.16.0:
+
+New in v0.16.0 (01.12.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.17.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.17.0:
+
+New in v0.17.0 (08.12.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.18.0.rst

@@ -0,0 +1,4 @@
+.. :CHANGE:v0.18.0:
+
+New in v0.18.0 (16.12.2015)
+================================================================================================================================================================

docs/ChangeLog/2015/v0.2.0.rst

@@ -0,0 +1,46 @@
+.. :CHANGE:v0.2.0:
+
+New in v0.2.0 (09.03.2015)
+================================================================================================================================================================
+
+* New packages:
+
+  * xil
+  * stream
+
+* New modules:
+
+  * PoC.bus - Modules for busses
+
+    * bus_Arbiter
+
+  * PoC.bus.stream - Modules for the PoC.Stream protocol
+
+    * stream_Buffer
+    * stream_DeMux
+    * stream_FrameGenerator
+    * stream_Mirror
+    * stream_Mux
+    * stream_Source
+
+  * PoC.misc.sync - Cross-Clock Synchronizers
+
+    * sync_Reset
+    * sync_Flag
+    * sync_Strobe
+    * sync_Vector
+    * sync_Command
+
+  * PoC.xil - Xilinx specific modules
+
+    * xil_SyncBits
+    * xil_SyncReset
+    * xil_BSCAN
+    * xil_Reconfigurator
+    * xil_SystemMonitor_Virtex6
+    * xil_SystemMonitor_Series7
+
+* Updated packages:
+
+  * utils
+  * arith