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This library is published and maintained by Chair for VLSI Design, Diagnostics
and Architecture - Faculty of Computer Science, Technische Universität Dresden,
Germany
http://tu-dresden.de/inf/vlsi-eda
PoC - "Pile of Cores" provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.
All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy.
Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based Infrastruture to offer a command line based frontend.
PoC's documentation is now hosted on ReadTheDocs.
| Version | Link | Build State |
|---|---|---|
| stable | http://poc-library.readthedocs.io/en/stable/ | |
| latest | http://poc-library.readthedocs.io/en/latest/ |