CSR: do not skip CSR instructions for mip

[poemonsense]

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[poemonsense]

#1538 introduces this line to mark CSR instructions targeting the mip register as "skip".

Here comes why at that time we thought it should be skipped. According to the RISC-V spec, MSIP is read-only in mip is written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts. That is, the MSIP bit is for IPI which is handled by external devices and thus cannot be simulated in a cycle-accurate manner in any reference model. Therefore, when MSIP is set and the user code tries to read MSIP, the co-simulation will abort due to different register file writeback data. In #1538, we think this is a typical use case for "skip", where external information is synced to the reference model.

However, skipping the mip CSR instructions bring another issue when mip is written with CSR instructions. For example, M-mode software may write the STIP field to raise a timer interrupt for S mode. If we skip this instruction, this CSR write instruction will not be executed and then we are having different MIP values for the DUT and REF.

So let's come back to the original MSIP case. It is an external bit, not in the architectural state of a processor, but affects only the read value of the MIP. Following the diff-rule based verification mechanism, we should copy the external states (which cannot be simulated accurately by the reference model) to the REF to avoid mismatches.

However, the MIP register has both architectural and non-architectural (external) states. We should skip only the external parts but keep the architectural states the same. This is a new case where the "skip" is not for all operations but only a part of the instruction. We may use a special bit to indicate the MIP operation. We may also think of other ways to do this.

This PR simply removes the "skip" sign for MIP CSR instructions. I don't know whether it can pass dual-core co-simulation. But generally speaking, the software should not read the MIP register to check the interrupts. Instead, it should check the mcause and interrupt controllers for the correct interrupt source. So if the software does not have the read-mip behavior, the co-simulation should work perfectly without "skip". Let's see whether the new OpenSBI+Linux will abort the co-simulation.

[poemonsense]

It's worth noting MIP has more external states, such as MEIP (is read-only in mip, and is set and cleared by a platform-specific interrupt controller), MTIP (is read-only in mip, and is cleared by writing to the memory-mapped machine-mode timer compare register), MEIP (discussed in the previous comment), SEIP (is writable in mip, and may be
written by M-mode software to indicate to S-mode that an external interrupt is pending. Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts. Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller), SSIP (writable in mip and may also be set to 1 by a platform-specific interrupt controller).

If we are going to implement the "partial skip" feature for MIP CSR instructions, must be careful on all conditions.