Add CoupledL2 with CHI interface #2953
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Enter `make verilog CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1` to compile XSTile of CHI version
This can make users to modify target format without recompiling scala.
This will make FIR elaboration much faster as discussed in #2951 Signed-off-by: Yangyu Chen <cyy@cyyself.name>
poemonsense
reviewed
May 8, 2024
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If there is no CHI Interconnect RTL for us now, should we develop a software co-simulation solution that simulates the interconnect part in software like gem5 for performance evaluation and functional check in CI? |
poemonsense
approved these changes
May 8, 2024
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[Generated by IPC robot]
master branch:
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The CHI interconnection is already in the planning phase. However, it will still take some time to complete. If there is support of software co-simulation for interconnection, it would be very welcome. |
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[Generated by IPC robot]
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[Generated by IPC robot]
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Diana0525
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that referenced
this pull request
May 17, 2024
This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are: * Fully coherent Request Node in a CHI interconnect. * Coherency granule of 64B cache line. * MESI cache coherence model, which is based on TileLink coherence policies. * Transition from TL-C transactions to CHI snoopable requests. * Transition from TL-UL transactions to CHI non-snoopable requests. * Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique. * Support for WriteNoSnp, WriteBackFull, Evict. * Support for all the snoops except for SnpDVMOp. * Request retry to manage protocol resources. * Message transfer across CHI interfaces based on Link Layer Credit. * Power aware signaling on the component interface. The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in [XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for now. TL2CHICoupledL2 is still not available for verilator simulation in this pr. To compile XSTile verilog with TL2CHICoupledL2, run `make verilog CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`. --------- Signed-off-by: Yangyu Chen <cyy@cyyself.name> Co-authored-by: Zhu Yu <yulightenyu@gmail.com> Co-authored-by: Tang Haojin <tanghaojin@outlook.com> Co-authored-by: Yangyu Chen <cyy@cyyself.name>
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This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are:
The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in XiangShan processor for now. TL2CHICoupledL2 is still not available for verilator simulation in this pr.
To compile XSTile verilog with TL2CHICoupledL2, run
make verilog CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1.