frontend：Merge frontend 20240401 #2948
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commit 5e916e7 Author: Easton Man <me@eastonman.com> Date: Tue Mar 5 19:43:21 2024 +0800 bpu: revert RegEnable on reset_u commit 37153f8 Author: Easton Man <me@eastonman.com> Date: Tue Mar 5 14:13:25 2024 +0800 bpu: remove LFSR clock gating commit 6cd72ef Author: Easton Man <me@eastonman.com> Date: Sat Mar 2 13:25:54 2024 +0800 bpu: use RegNextWithEnable in Valid[T] commit e6b2fa7 Author: Easton Man <me@eastonman.com> Date: Fri Mar 1 16:41:21 2024 +0800 bpu: fix missing control sig some control signal inside Tage is using data signals from io this commit add io control to these signals commit 09cf425 Author: Easton Man <me@eastonman.com> Date: Fri Mar 1 15:38:31 2024 +0800 bpu: port clock gating opt from nanhu this commit ports clock gating optimization from nanhu if applicable, most ungated register is opted Co-authored-by: Liang Sen <liangsen20z@ict.ac.cn>
commit b42b57f Author: ngc7331 <ngc7331@outlook.com> Date: Fri Mar 1 18:09:59 2024 +0800 Bump utility commit 8289b1a Author: Liang Sen <liangsen20z@ict.ac.cn> Date: Tue Aug 16 10:58:09 2022 +0800 ICache: Clock gating optimization cherry-picked e9ef1b0 commit 6239112 Author: Liang Sen <liangsen20z@ict.ac.cn> Date: Mon Aug 15 17:32:57 2022 +0800 ICache: Clock gating optimization cherry-picked 1de1aa1 commit 7b6d1db Author: Liang Sen <liangsen20z@ict.ac.cn> Date: Tue Aug 16 10:33:13 2022 +0800 IFU: Clock gating optimization cherry-picked 0f65b04
commit 8a573db Author: Easton Man <me@eastonman.com> Date: Fri Mar 15 21:23:11 2024 +0800 ftq: fix ftb_entry_mem #0 port assign commit 7ce653a Author: Easton Man <me@eastonman.com> Date: Fri Mar 15 21:22:15 2024 +0800 ftq: use RegEnable instead in anonymous RegNext commit f34a341 Author: Easton Man <me@eastonman.com> Date: Wed Mar 6 15:17:16 2024 +0800 ftq: ftb_entry_mem ren problem work around commit 6de13bd Author: Easton Man <me@eastonman.com> Date: Tue Mar 5 21:22:54 2024 +0800 ftq: fix reset assertion commit 23c57fe Author: Easton Man <me@eastonman.com> Date: Tue Mar 5 21:11:11 2024 +0800 ftq: fix commitStateQueue update status commit fd86e7a Author: Easton Man <me@eastonman.com> Date: Tue Mar 5 15:15:41 2024 +0800 ftq: port nanhu clock gating Co-authored-by: Liang Sen <liangsen20z@ict.ac.cn>
commit 7cb9848 Author: Easton Man <me@eastonman.com> Date: Fri Mar 15 23:18:21 2024 +0800 bpu: gate s0 registers when s0_stall
ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken
ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS
ftq_redirect_sram->ftq_redirect_mem
Co-authored-by: chenguokai <chenguokai17@mails.ucas.ac.cn>
dlt folded_hist/afhob/lastBrNumOH ftq_redirect_mem: 247*64->73*64
This PR added RISC-V Integer Conditional Operations Extension, which is in the RVA23U64 Profile Mandatory Base. And the performance of conditional move instructions in micro-architecture is an interesting point to explore. Zicond instructions added: czero.eqz, czero.nez Changes based on spec: https://github.com/riscvarchive/riscv-zicond/releases/download/v1.0.1/riscv-zicond_1.0.1.pdf Signed-off-by: Yangyu Chen <cyy@cyyself.name>
sleep-zzz
requested review from
chenguokai,
ssszwic,
Gao-Zeyu and
eastonman
as code owners
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[Generated by IPC robot]
master branch:
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