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New out-of-order vlsu for better vector performance #2944

Merged
merged 163 commits into from
May 21, 2024
Merged

New out-of-order vlsu for better vector performance #2944

merged 163 commits into from
May 21, 2024

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good-circle
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@good-circle good-circle commented May 4, 2024 •
edited

Support out-of-order non-Segment Unit-Strdie load/store instructions
Support out-of-order non-Segment Stride load/store instructions
Support out-of-order non-Segment Order/Unorder Index load/store instructions
Use LSQ to ensure memory access order of order index instructions
Use FSM to achieve Segment Load/Store instructions, which can ensure segment access order

TODO: Except Segment order index, other segment instructions can execute out-of-order, don't need to use FSM to ensure memory access order.

Ziyue-Zhang and others added 30 commits March 18, 2024 17:34
@Ziyue-Zhang @xiaofeibao-xjtu
float: fix read rouding mode which is ecnoded in the float instruction
824af1e
@Ziyue-Zhang @xiaofeibao-xjtu
float: use VCVT module for all fcvt instructions
34f9ccd 
Co-authored-by: chengguanghui <wissycgh@gmail.com>
@lewislzh
remove isreverse from vecfuncunit
783a1d5 
delete uuid
@wissygh
CSR: fix dcsr.cause when hart enter debug mode according to ebreak in…
36040c6 
…struction
@Ziyue-Zhang
rv64v: replace all i2f move instructions to i2v instructions
964d9a8
@Tang-Haojin
ClockGate: remove @* after always_latch
66a315f
@sinsanction @xiaofeibao-xjtu
WBArbiter: fix full check of cancel counter
cbe9b53
@sinsanction @xiaofeibao-xjtu
Parameters: fix the count of vector read ports
fc605fc
@sinsanction @xiaofeibao-xjtu
WbDataPath: better signal connection in WbDataPath
6d11c05
@sinsanction @xiaofeibao-xjtu
WbDataPath: add 1 cycle delay when vf exe units write back to int reg…
2e49ee7 
…file
@sinceforYy @xiaofeibao-xjtu
FuConfig: add one cycle to vppu
b547426
@sinceforYy @xiaofeibao-xjtu
bump yunsuan
3f6bc9b
@wissygh
Trigger: delete chain betweem inst trigger and mem trigger
f914565
@lewislzh
fix vipu timing (#2809)
0202938 
* remove isreverse from vecfuncunit

* fix a bug: first uop of vrsub donot need reverse; delete uuid

* fix vipu timing : add one cycle delay to vmask and reduction

* add yunsuan change
@weidingliu
rv64v: add suport of 128-bit vector elements load/store
00e6f2e
@weidingliu @good-circle
rv64v: rewrite VLSU
3952421 
uop split in V*SplitImp, flow merge in V*MergeBufferImp, uop issued out of order
@Anzooooo @good-circle
rv64v: add support for vlsu continuous 'uop' (#2816)
f3a9fb0 
add LSQ backpressure logic and 'uop' continuous application LSQ entries logic
@good-circle
rv64v: implement lsu & lsq vector datapath
26af847
@huxuan0307 @good-circle
Backend: support vector load&store better
6dbb4e0 
* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs
@Anzooooo @good-circle
rv64v: fix calculation of 'numLsElem' (#2823)
1503b10
@Anzooooo @good-circle
VLSU: fix allocated LSQ entries (#2829)
3ea758f
@weidingliu @good-circle
VLSU: fix bugs of build and connect
b761869
@weidingliu @good-circle
VSplit: fix enqueue condition
a8e777e
@weidingliu @good-circle
VSplit: fix flowNum calculate
00b107d
@weidingliu @good-circle
VLSU: add support that replay vector load mask
375ed6a
@weidingliu @good-circle
Dispatch2Iq,VLSU: fix uop of flowNum
b9b5052
@weidingliu @good-circle
VSplit: fix calculation of strideOffsetReg
5281d28
@weidingliu @good-circle
VMergeBuffer: fix bug of uopWriteback
84ddb80
@weidingliu @good-circle
VLSU: fix bug of writeback mask
1d61920
@weidingliu @good-circle
VLSU: fix read/write mask
6bd8baa
Anzooooo and others added 5 commits May 15, 2024 20:56
@Anzooooo @good-circle
StoreQueue: fix the bug of addrReadyVec.
df87387 
This commit fix the situation that inactive element will not send to pipeline, which cause stAddrReadyVec always false.
@Ziyue-Zhang @good-circle
rv64v: set vector segment indexed store instrucion's vecwen to false
7635b2a
@Ziyue-Zhang @good-circle
rv64v: fix the logic of writing vtype for vsetvl instruction
550efd1
@Ziyue-Zhang @good-circle
vtype: fix walk vtype and commit vtype update when state is special walk
dd40232
@weidingliu @good-circle
MinimalConfig: increase the number of issue queue entries
45619a2 
Because segment instructions may send 8 uop to issue queue in order by enq 0. However, excluding enq 1, issue queue only have 7 entries.
@XiangShanRobot
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[Generated by IPC robot]
commit: 29ca19d

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
29ca19d 1.857 0.449 2.091 1.188 2.476 2.588 2.331 0.956 1.392 1.365 3.124 2.630 2.432 2.954

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c83747b
d7a3496
5961467 1.855 0.450 2.103 1.177 2.478 2.594 2.333 0.957 1.398 1.421 3.117 2.655 2.454 2.952
4b40434
9eee369 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
006b878 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
7299828 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
0c70648 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
b628978 1.854 0.450 2.103 1.190 2.468 2.593 2.329 0.960 1.377 1.427 3.123 2.639 2.451 2.960
5e237ba 0.450 2.103 2.328 1.377 2.639

@XiangShanRobot
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[Generated by IPC robot]
commit: d5fb5cf

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
d5fb5cf 1.857 0.449 2.091 1.188 2.476 2.588 2.331 0.956 1.392 1.365 3.124 2.630 2.432 2.954

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c83747b 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
d7a3496 1.855 0.450 2.103 1.177 2.478 2.594 2.332 0.957 1.398 1.421 3.117 2.655 2.454 2.952
5961467 1.855 0.450 2.103 1.177 2.478 2.594 2.333 0.957 1.398 1.421 3.117 2.655 2.454 2.952
4b40434
9eee369 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
006b878 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
7299828 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
0c70648 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
b628978 1.854 0.450 2.103 1.190 2.468 2.593 2.329 0.960 1.377 1.427 3.123 2.639 2.451 2.960
5e237ba 0.450 2.103 2.328 1.377 2.639

@good-circle good-circle marked this pull request as ready for review May 17, 2024 02:56
@good-circle good-circle requested a review from linjuanZ May 17, 2024 02:56
@good-circle good-circle changed the title New vlsu New out-of-order vlsu for better performance May 17, 2024
@good-circle good-circle changed the title New out-of-order vlsu for better performance New out-of-order vlsu for better vector performance May 17, 2024
@Anzooooo Anzooooo changed the title New out-of-order vlsu for better vector performance New out-of-order vlsu for better vector performance" May 17, 2024
@weidingliu
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  • Support out-of-order non-Segment Unit-Strdie load/store instructions
  • Support out-of-order non-Segment Stride load/store instructions
  • Support out-of-order non-Segment Order/Unorder Index load/store instructions
  • Use LSQ to ensure memory access order of order index instructions
  • Use FSM to achieve Segment Load/Store instructions, which can ensure segment access order
    
    TODO: Except Segment order index, other segment instructions can execute out-of-order, don't need to use FSM to ensure memory access order.

@Anzooooo Anzooooo changed the title New out-of-order vlsu for better vector performance" New out-of-order vlsu for better vector performance May 17, 2024
@weidingliu weidingliu self-requested a review May 17, 2024 10:34
@good-circle good-circle mentioned this pull request May 20, 2024
Merged
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[Generated by IPC robot]
commit: c11f007

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
c11f007 1.857 0.449 2.091 1.188 2.476 2.588 2.331 0.956 1.392 1.365 3.124 2.630 2.432 2.954

master branch:

commit astar copy_and_run coremark gcc gromacs lbm linux mcf microbench milc namd povray wrf xalancbmk
2316cea 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
e778bb8 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
c83747b 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
d7a3496 1.855 0.450 2.103 1.177 2.478 2.594 2.332 0.957 1.398 1.421 3.117 2.655 2.454 2.952
5961467 1.855 0.450 2.103 1.177 2.478 2.594 2.333 0.957 1.398 1.421 3.117 2.655 2.454 2.952
4b40434 1.855 0.450 2.103 1.177 2.478 2.594 2.328 0.957 1.398 1.421 3.117 2.655 2.454 2.952
9eee369 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
006b878 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
7299828 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960
0c70648 1.854 0.450 2.103 1.190 2.468 2.593 2.330 0.960 1.377 1.427 3.123 2.639 2.451 2.960

@Tang-Haojin Tang-Haojin merged commit 9f2c7f7 into master May 21, 2024
4 checks passed
@Tang-Haojin Tang-Haojin deleted the vlsu-merge-master-0504 branch May 21, 2024 01:20
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@Tang-Haojin Tang-Haojin Tang-Haojin approved these changes

@linjuanZ linjuanZ Awaiting requested review from linjuanZ

@huxuan0307 huxuan0307 Awaiting requested review from huxuan0307

@Anzooooo Anzooooo Awaiting requested review from Anzooooo

@Ziyue-Zhang Ziyue-Zhang Awaiting requested review from Ziyue-Zhang

@weidingliu weidingliu Awaiting requested review from weidingliu

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