Skip to content

Issues: Nic30/hdlConvertor

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

30 Open 102 Closed
30 Open 102 Closed
Author
Filter by author
Label
Filter by label
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Milestones
Filter by milestone
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Prebuilt Binary Release to PyPi
#187 opened Jan 5, 2024 by khwong-c v2.4
8
(System)Verilog parallel_case attribute is not supported
#185 opened Oct 17, 2023 by KatCe
1
CMake install DIRECTORY include wrong parameters?
#182 opened Jun 13, 2023 by liuzikai v2.4
2
Using updated SV/Verilog, VHDL Grammars
#178 opened Apr 17, 2023 by AmeyaVS
2
Updating Git Submodules For Tests
#177 opened Apr 16, 2023 by AmeyaVS
1
Verilog2017 - unpacked array converted as packed
#169 opened Jun 14, 2022 by diffore
2
Convert VHDL package to Verilog or SV
#168 opened Apr 5, 2022 by jabate-anova
2
incorrect Position
#166 opened Feb 5, 2022 by Thomasb81
5
Preprocessor - expose complete parser?
#165 opened Dec 24, 2021 by the-moog
11
Handling extraneous commas (SystemVerilog)
#163 opened Nov 26, 2021 by the-moog
1
Replace scikit-build/cmake with mesonpep517/meson (potential drop of python2.7 support)
#162 opened Nov 20, 2021 by Nic30
1
SV grammar hirarchical identifier in delay_value rule
#160 opened Oct 20, 2021 by Thomasb81
SystemVerilog import package - doesn't seem to do anything?
#149 opened Jan 26, 2021 by flemish4
8
VHDL: proper tests for comment parsing
#148 opened Jan 22, 2021 by Nic30
VHDL: Arrays of unbounded elements not working correctly.
#141 opened Oct 10, 2020 by mewais
VHDL: Slicing and range attributes incorrectly identified as function calls.
#140 opened Oct 7, 2020 by mewais
13
Package Instantiation in VHDL
#136 opened Aug 27, 2020 by mewais
2
Add file name to CodePosition
#134 opened Aug 26, 2020 by tictacmenthe
5
BLIF support
#132 opened Jul 27, 2020 by mewais
7
notebooks with examples
#131 opened Jun 19, 2020 by Nic30
Optional compiler directives
#99 opened Nov 24, 2019 by Thomasb81
1
Elaboration?
#96 opened Nov 14, 2019 by hs-apotell
19
Support for static library build
#95 opened Nov 14, 2019 by hs-apotell
5
finish the integration with sv-tests
#92 opened Nov 13, 2019 by Nic30
1
proper support for begin_keywords-end_keywords directive
#91 opened Nov 13, 2019 by Nic30
ProTip! Mix and match filters to narrow down what you’re looking for.