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SystemVerilog import package - doesn't seem to do anything? #149

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flemish4 opened this issue Jan 26, 2021 · 8 comments
Open

SystemVerilog import package - doesn't seem to do anything? #149

flemish4 opened this issue Jan 26, 2021 · 8 comments

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@flemish4
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Hi,
I'm trying to use hdlConvertor to discover all the files I need in my file list. (If someone has already done this please let me know :) )

So far I'm checking the error messages for missing includes directories and I'm looking for hdlAst._structural.HdlCompInst to get modules which are needed. Then I'm exploring the hierarchy and checking each module file found. This seems to work well.

The one thing that is missing is where there is an 'import something_pkg::*; this doesn't appear in the parsed object at all.
Then on lines where it is used there is just a double colon operator.

At no point does it realize that a file is missing.
Is this expected behaviour?

Thanks

@Nic30
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Nic30 commented Jan 26, 2021

There was a missing conversion, it should be fixed now.
1cd4910#diff-d524652fb3a0f07012fd10ec301daeaea5e2ea5fc6125431a4d9f38e962073a5

Nic30/hdlConvertorAst@ceaa80f

@flemish4
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Wow that was quick!
Thanks for the fix, I'll check it asap.

@flemish4
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That looks to work well thanks, I can now extract the packages that are used.
It has revealed one more issue though - it seems that package declarations are not yet supported, is this planned?
"Source_textParser.visitDescription.package_declaration Conversion to Python object not implemented"

I have nested packages so this looks like the last hurdle to full file list generation :)

@Thomasb81
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I guess contribution are welcome.

Basically :
implement antlr visitePackage_declaration method and other visit* method relevant for your application in cpp.
Fill structure with data you want to collect and make it available into python world.
Implement unit test could help to preserve feature over tool change.

1cd4910 commit could be a useful source of inspiration.

@flemish4
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flemish4 commented Jan 27, 2021 via email

@flemish4
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flemish4 commented Jan 27, 2021 via email

@Thomasb81
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I don't think so.
That's why the tool can emit such message : "Source_textParser.visitDescription.package_declaration Conversion to Python object not implemented" at some place to point the limitation.

@Nic30
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Nic30 commented Jan 27, 2021

All things which are not converted to python yet are marked with NotImplementedLogger::print

NotImplementedLogger::print(

The problem is that the verilog/vhdl/systemverilog contains ridiculous amount of deprecated things. Most of the things were implemented on demand. Adding new things is simple, but we prefer to simplify HDL syntax obscurities so we do not need to deal with them later.

If you do not like it you can use antlr grammars or c++ directly, but remember that there is a reason for this conversion and that is to remove a bloat and obscurities and you will have to deal with this obscurities if you use "base SV parser".

If you can help it would be nice.

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