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grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.

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Grape

Implementation of single cycle RISC-V processor, this is a tiny implementation without CSRs!

Please checkout my Quark project which is a riscv processor that fully complies to the spec with CSRs, GPIO and a UART module connected to it so one can tinker around with it.

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Datapath Schematic

datapath

Control Path Schematic:

ctr_path

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grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.

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