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My Bachelor's Thesis "Optimizing Ascon for 32-bit Architectures, Fast Implementations for RISC-V and Xtensa"

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Optimizing Ascon for 32-bit Architectures, Fast Implementations for RISC-V and Xtensa

This repository contains my Bachelor's Thesis and the optimized implementations of Ascon that I created for the thesis.

Thesis

The Bachelor's Thesis is available in thesis.pdf.

Implementations

NameArchitectureStrategyNotes
ESP32
c_opt64_lowsizeXtensa LX6shiftAscon-C
c_opt64Xtensa LX6shiftAscon-C
asm_xtensa_bi32_ror*Xtensa LX6bit-interleaved, ror
asm_xtensa_fsr*Xtensa LX6fsr
ESP32-C3
c_opt64_lowsizeRISC-V 32-bitshiftAscon-C
c_opt64RISC-V 32-bitshiftAscon-C
asm_rv32_camposRISC-V 32-bitshiftCampos et al.
asm_rv32_shift*RISC-V 32-bitshift
riscvOVPsim+
c_opt64_lowsizeRISC-V 32-bitshiftAscon-C
c_opt64RISC-V 32-bitshiftAscon-C
asm_rv32_camposRISC-V 32-bitshiftCampos et al.
asm_rv32_shift*RISC-V 32-bitshift
asm_rv32_Zbb_shift*+Zbbshiftwith andn, orn, ror, rev8
asm_rv32_Zbb_bi32_ror*+Zbbbit-interleaved, rorwith andn, orn, ror, rev8
asm_rv32_Zbkb_bi32_ror*+Zbkbbit-interleaved, rorwith zip, unzip, pack
asm_rv32_Zbp_bi32_ror*+Zbpbit-interleaved, rorwith packu
asm_rv32_Zbt_fsr*+Zbtfsrwith fsr

Implementations marked with * are new implementations. All implementations implement Ascon128a, Ascon128, Ascon80pq, AsconHash, AsconHasha, AsconXof, and AsconXofa, except asm_rv32_campos, which only implements Ascon128a.

Benchmark Results

The benchmarking framework that was created for this thesis is available here.

Performance in cycles per byte, for long inputs (32 kB)
NameAscon128aAscon128AsconHashaAsconHash
Ascon80pqAsconXofaAsconXof
ESP32
c_opt64_lowsize98.76 c/B141.53 c/B178.04 c/B260.14 c/B
c_opt6485.01 c/B127.49 c/B156.95 c/B230.07 c/B
asm_xtensa_bi32_ror*70.87 c/B100.09 c/B115.47 c/B166.54 c/B
asm_xtensa_fsr*51.01 c/B77.18 c/B95.68 c/B139.24 c/B
ESP32-C3
c_opt64_lowsize78.35 c/B112.81 c/B140.88 c/B205.97 c/B
c_opt6470.83 c/B102.90 c/B129.44 c/B194.27 c/B
asm_rv32_campos70.13 c/Bn/an/an/a
asm_rv32_shift*66.30 c/B97.35 c/B124.00 c/B183.34 c/B
riscvOVPsim+
c_opt64_lowsize76.18 c/B110.36 c/B138.66 c/B202.70 c/B
c_opt6468.85 c/B101.10 c/B128.15 c/B189.69 c/B
asm_rv32_campos68.79 c/Bn/an/an/a
asm_rv32_shift*64.79 c/B94.85 c/B121.17 c/B179.72 c/B
asm_rv32_Zbb_shift*58.65 c/B87.59 c/B114.91 c/B171.46 c/B
asm_rv32_Zbb_bi32_ror*54.71 c/B74.45 c/B84.87 c/B122.40 c/B
asm_rv32_Zbkb_bi32_ror*41.44 c/B61.19 c/B78.23 c/B115.77 c/B
asm_rv32_Zbp_bi32_ror*40.94 c/B60.69 c/B77.98 c/B115.52 c/B
asm_rv32_Zbt_fsr*38.62 c/B57.56 c/B74.85 c/B111.39 c/B
Performance in cycles per byte, for short inputs (16 B)
NameAscon128aAscon128AsconHashaAsconHash
Ascon80pqAsconXofaAsconXof
ESP32
c_opt64918.61 c/B874.50 c/B564.61 c/B760.94 c/B
c_opt64_lowsize398.83 c/B441.23 c/B588.36 c/B793.44 c/B
asm_xtensa_bi32_ror*293.27 c/B310.49 c/B442.69 c/B595.77 c/B
asm_xtensa_fsr*214.51 c/B239.00 c/B365.68 c/B496.25 c/B
ESP32-C3
c_opt641548.91 c/B942.02 c/B902.54 c/B7484.96 c/B
c_opt64_lowsize320.40 c/B354.51 c/B472.86 c/B635.43 c/B
asm_rv32_campos303.58 c/Bn/an/an/a
asm_rv32_shift*273.79 c/B301.60 c/B471.46 c/B649.71 c/B
riscvOVPsim+
c_opt64_lowsize310.37 c/B344.30 c/B461.14 c/B621.14 c/B
asm_rv32_campos285.71 c/Bn/an/an/a
c_opt64277.21 c/B307.99 c/B431.01 c/B584.95 c/B
asm_rv32_shift*265.59 c/B292.46 c/B459.70 c/B635.20 c/B
asm_rv32_Zbb_shift*240.77 c/B268.84 c/B435.08 c/B604.58 c/B
asm_rv32_Zbb_bi32_ror*222.52 c/B231.87 c/B325.01 c/B437.51 c/B
asm_rv32_Zbkb_bi32_ror*172.71 c/B190.46 c/B298.51 c/B411.01 c/B
asm_rv32_Zbp_bi32_ror*170.84 c/B189.27 c/B297.51 c/B410.01 c/B
asm_rv32_Zbt_fsr*160.77 c/B178.84 c/B285.08 c/B394.58 c/B
Performance difference in percent, for long inputs (32 kB)
Name Ascon128a Ascon128 AsconHasha AsconHash
Ascon80pq AsconXofa AsconXof
ESP32
c_opt64_lowsize $\color{red}\text{+13.93 \%}$ $\color{red}\text{+9.92 \%}$ $\color{red}\text{+11.84 \%}$ $\color{red}\text{+11.56 \%}$
c_opt64 ref ref ref ref
asm_xtensa_bi32_ror* $\color{green}\text{-19.95 \%}$ $\color{green}\text{-27.38 \%}$ $\color{green}\text{-35.93 \%}$ $\color{green}\text{-38.15 \%}$
asm_xtensa_fsr* $\color{green}\text{-66.65 \%}$ $\color{green}\text{-65.19 \%}$ $\color{green}\text{-64.04 \%}$ $\color{green}\text{-65.23 \%}$
ESP32-C3
c_opt64_lowsize $\color{red}\text{+10.50 \%}$ $\color{red}\text{+8.79 \%}$ $\color{red}\text{+8.12 \%}$ $\color{red}\text{+5.68 \%}$
c_opt64 $\color{red}\text{+0.99 \%}$ ref ref ref
asm_rv32_campos ref n/a n/a n/a
asm_rv32_shift* $\color{green}\text{-5.77 \%}$ $\color{green}\text{-5.70 \%}$ $\color{green}\text{-4.39 \%}$ $\color{green}\text{-5.96 \%}$
riscvOVPsim+
c_opt64_lowsize $\color{red}\text{+9.69 \%}$ $\color{red}\text{+8.39 \%}$ $\color{red}\text{+7.58 \%}$ $\color{red}\text{+6.42 \%}$
c_opt64 $\color{red}\text{+0.08 \%}$ ref ref ref
asm_rv32_campos ref n/a n/a n/a
asm_rv32_shift* $\color{green}\text{-6.19 \%}$ $\color{green}\text{-6.59 \%}$ $\color{green}\text{-5.76 \%}$ $\color{green}\text{-5.55 \%}$
asm_rv32_Zbb_shift* $\color{green}\text{-17.29 \%}$ $\color{green}\text{-15.43 \%}$ $\color{green}\text{-11.52 \%}$ $\color{green}\text{-10.63 \%}$
asm_rv32_Zbb_bi32_ror* $\color{green}\text{-25.75 \%}$ $\color{green}\text{-35.79 \%}$ $\color{green}\text{-51.00 \%}$ $\color{green}\text{-54.97 \%}$
asm_rv32_Zbkb_bi32_ror* $\color{green}\text{-66.01 \%}$ $\color{green}\text{-65.23 \%}$ $\color{green}\text{-63.80 \%}$ $\color{green}\text{-63.85 \%}$
asm_rv32_Zbp_bi32_ror* $\color{green}\text{-68.04 \%}$ $\color{green}\text{-66.59 \%}$ $\color{green}\text{-64.33 \%}$ $\color{green}\text{-64.21 \%}$
asm_rv32_Zbt_fsr* $\color{green}\text{-78.12 \%}$ $\color{green}\text{-75.65 \%}$ $\color{green}\text{-71.20 \%}$ $\color{green}\text{-70.30 \%}$
Performance difference in percent, for short inputs (16 B)
Name Ascon128a Ascon128 AsconHasha AsconHash
Ascon80pq AsconXofa AsconXof
ESP32
c_opt64 $\color{red}\text{+56.58 \%}$ $\color{red}\text{+49.54 \%}$ ref ref
c_opt64_lowsize ref ref $\color{red}\text{+4.04 \%}$ $\color{red}\text{+4.10 \%}$
asm_xtensa_bi32_ror* $\color{green}\text{-35.99 \%}$ $\color{green}\text{-42.11 \%}$ $\color{green}\text{-27.54 \%}$ $\color{green}\text{-27.72 \%}$
asm_xtensa_fsr* $\color{green}\text{-85.93 \%}$ $\color{green}\text{-84.61 \%}$ $\color{green}\text{-54.40 \%}$ $\color{green}\text{-53.34 \%}$
ESP32-C3
c_opt64 $\color{red}\text{+80.40 \%}$ $\color{red}\text{+62.37 \%}$ $\color{red}\text{+47.61 \%}$ $\color{red}\text{+91.51 \%}$
c_opt64_lowsize $\color{red}\text{+5.25 \%}$ ref ref ref
asm_rv32_campos ref n/a n/a n/a
asm_rv32_shift* $\color{green}\text{-10.88 \%}$ $\color{green}\text{-17.54 \%}$ $\color{green}\text{-0.30 \%}$ $\color{red}\text{+2.20 \%}$
riscvOVPsim+
c_opt64_lowsize $\color{red}\text{+10.68 \%}$ $\color{red}\text{+10.55 \%}$ $\color{red}\text{+6.53 \%}$ $\color{red}\text{+5.83 \%}$
asm_rv32_campos $\color{red}\text{+2.98 \%}$ n/a n/a n/a
c_opt64 ref ref ref ref
asm_rv32_shift* $\color{green}\text{-4.38 \%}$ $\color{green}\text{-5.31 \%}$ $\color{red}\text{+6.24 \%}$ $\color{red}\text{+7.91 \%}$
asm_rv32_Zbb_shift* $\color{green}\text{-15.13 \%}$ $\color{green}\text{-14.57 \%}$ $\color{red}\text{+0.93 \%}$ $\color{red}\text{+3.25 \%}$
asm_rv32_Zbb_bi32_ror* $\color{green}\text{-24.58 \%}$ $\color{green}\text{-32.83 \%}$ $\color{green}\text{-32.61 \%}$ $\color{green}\text{-33.70 \%}$
asm_rv32_Zbkb_bi32_ror* $\color{green}\text{-60.51 \%}$ $\color{green}\text{-61.71 \%}$ $\color{green}\text{-44.39 \%}$ $\color{green}\text{-42.32 \%}$
asm_rv32_Zbp_bi32_ror* $\color{green}\text{-62.27 \%}$ $\color{green}\text{-62.72 \%}$ $\color{green}\text{-44.87 \%}$ $\color{green}\text{-42.67 \%}$
asm_rv32_Zbt_fsr* $\color{green}\text{-72.42 \%}$ $\color{green}\text{-72.22 \%}$ $\color{green}\text{-51.19 \%}$ $\color{green}\text{-48.25 \%}$

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My Bachelor's Thesis "Optimizing Ascon for 32-bit Architectures, Fast Implementations for RISC-V and Xtensa"

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