AArch32: vmvn had incorrect double-word order and number of bytes provided instead of bits in bitwise left shift #6544
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed an unexpected behaviour in the
vmvn
instruction for both, AArch32 (ARM:LE:32:v8
) & Thumb (ARM:LE:32:v8T
).According to the manual, it takes a value from a register, inverts the value of each bit, and places the result in the destination register. However, we noticed the output was incorrect.
e.g, for AArch32 with,
Instruction:
0xe005f0f3, vmvn q8,q8
initial_registers:
{ "q8": 0xffffffffffffffff }
We get:
Hardware:
{ "q8": 0xffffffffffffffff0000000000000000 }
Patched Spec:
{ "q8": 0xffffffffffffffff0000000000000000 }
Existing Spec:
{ "q8": 0xffffffffffffffff }
e.g, for Thumb with,
Instruction:
0xf0ffe005, vmvn q8,q8
initial_registers:
{ "q8": 0x0 }
We get:
Hardware:
{ "q8": 0xffffffffffffffffffffffffffffffff }
Patched Spec:
{ "q8": 0xffffffffffffffffffffffffffffffff }
Existing Spec:
{ "q8": 0xffffffffffffffffff }
Note: The patched spec does not introduce any disassembly changes to the best of our knowledge.