AArch64: Fix fmla and fmls element count and size for halfword cases #6543
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GhidorahRex
added
Type: Bug
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As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the fmla and fmls instructions for AARCH64. According to Sections C7.2.122 and C7.2.126, the expected behaviour is operate on 16 bit floats when the 4H or 8H registers are used. While the current behaviour instead treats adjacent pairs of 16 bit floats as a single 32 bit float.
e.g.:
0xe70e410e"fmla v7.4H, v23.4H, v1.4H" with z7=0x82ce9a6474c3d5fa, z23=0x63518afba03f54aa and z1=0x7223a9bdc6af50c8Hardware Reference: z7 = 0x7c009a5f74c36963
Existing Spec: z7 = 0x7f80000074c3d5fa
Patched Spec: z7 = 0x7c009a5f74c36963