AArch32: vdup had destructive bitwise AND operations instead of OR and missing Thumb constructor constraints #6542
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* 8byte vector duplication to 16byte performed bitwise AND (destructive) instead of OR of the 8byte shifted results, causing all 16byte vector duplications to be 0 * non-thumb constraints were used in a thumb instruction, added thumb specific constraints and separated them using TMode ctx field
GhidorahRex
added
Type: Bug
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As part of a research project testing the accuracy of the SLEIGH specifications compared to real hardware, we observed an unexpected behaviour in the
vdupinstruction for both, AArch32 (ARM:LE:32:v8) & Thumb (ARM:LE:32:v8T).According to the manual, it duplicates a single element of a vector/general-purpose register into every element of the destination vector. However, we noticed the output was incorrect. This was due to destructive bitwise AND operations instead of OR & missing thumb constructor constraints causing a thumb instruction to execute like AArch32 instruction.
e.g, for AArch32 with,
Instruction:
0x600cf1f3, vdup.8 q8,d16[0x0]initial_registers:
{ "q8": 0xdf60afddae76036c20f35d532cdd79eb }We get:
Hardware:
{ "q8": 0xebebebebebebebebebebebebebebebeb }Patched Spec:
{ "q8": 0xebebebebebebebebebebebebebebebeb }Existing Spec:
{ "q8": 0x0 }and,
Instruction:
0x900ba0be, vduplt.32 q8,r0initial_registers:
{ "r0": 0x80, "NG": 0x1, "OV": 0x0 }We get:
Hardware:
{ "q8": 80000000800000008000000080 }Patched Spec:
{ "q8": 80000000800000008000000080 }Existing Spec:
{ "q8": 0x0 }e.g, for Thumb with,
Instruction:
0xa0ee900b, vdup.32 q8,r0initial_registers:
{ "r0": 0xd1c8a9dc, "lr": 0xaa41700d }We get:
Hardware:
{ "q8": 0xd1c8a9dcd1c8a9dcd1c8a9dcd1c8a9dc }Patched Spec:
{ "q8": 0xd1c8a9dcd1c8a9dcd1c8a9dcd1c8a9dc }Existing Spec (with AND/OR fix):
{ "q8": 0x700d700d700d700d700d700d700d700d }Existing Spec:
{ "q8": 0x0 }Note: The patched spec does introduce disassembly changes for the patched thumb variant. (eg, 0xa0ee900b is vdup.32 q8,r0 instead of vdup.32 q8,lr in Thumb.)