Test bench to measure and investigate performance of Apache Maven project

LIN (Local Interconnect Network) bus protocol, a serial communication protocol for automotive applications.

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

High speed C/C++ based behavioural Verilog memory model

VLSI System Design Practice Lab

Hosting all of my ZeroBraine Lua projects

Simple equalization circuit specified using VHDL

A VHDL implementation of Finite State Machines (FSM) and reverse engineering other hidden FSMs

Test bench to develop a 16b fixed point PID class for OrangeBot

VHDL assignments done at @ufms.

Circuito combinacional con entrada de 4 bits (número sin signo en binario puro) y salida con un número de 4 bits, su valor es redondear la operación 4 x RAIZ CUADRADA(y) al entero más próximo. El circuito se diseña de diversas maneras, cada una con una descripción en VHDL como arquitectura de la entidad.

Solutions to C exam past paper questions and C assignments 📂

Design and build a PCB shield including a low-tech graphite strain sensor coupled to an analog electronic circuit that communicate data via a microcontroller to an Android application

📋 List of practical and laboratory works from Hardware&Software Development subject from university

Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.