A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

5-stage pipelined 32-bit MIPS microprocessor in Verilog

It's all coming back into focus!

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Linux kernel source tree with the latest features and modifications to unleash the full potential of Ingenic processors.

Some of my assembly code (examples, iterative and recursive algorithms) from Computer's Architecture course in Sapienza University, CS Bachelor's Degree 💾

A 5-stage pipelined mips32 processor

A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog

Modification of the MARS program originally written by Kenneth Vollmar and Pete Sanderson at Missouri State University.

A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.

MIPS simulator written in Go

Solution for the assignment in Digital Design and Computer Architecture course including test benches running faster than official nightly tests.

An ELF parser, which calculates stack usage for embedded mips microcontroller, especially for Microchip's XC32 compiler

🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

🔮 A 32-bit MIPS Processor Implementation in Verilog HDL

A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.

DEPRECATED!!! An (almost) fully functional theme engine for MARS.

💻 MIPS Pipeline Processor simulator

A complete classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.