💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
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Updated
Jan 20, 2024 - Rust
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
Database of CPU Opcodes
HF-RISC SoC
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…
Rust implementation of AluVM (RISC functional machine)
UME::SIMD A library for explicit simd vectorization.
🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.
RISC-V Assembly code assembler package for Python.
XCrypto: a cryptographic ISE for RISC-V
RISC-V Assembly code assembler package for Python.
SCARV: a side-channel hardened RISC-V platform
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Advanced Matrix Extensions (AMX) Guide
Kite: Architecture Simulator for RISC-V Instruction Set
Super scalar Processor design
Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.
Instruction Set Architecture Description Format
ARM Multicycle Processor - 32 bit Assembly instructions - VHDL - Arithmetic and Logical operations, Memory read and write - Vivado
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
💾 The LC3 virtual machine
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