Nix derivations for EDA tools

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

En este proyecto yo hice el rediseño (electrónico y programas), así como modificaciones del sistema de auto alarma previamente implementado por la empresa, solucionando los problemas de consumo de energía y mejorando el circuito funcional (la parte automática) con un rediseño total.

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the Design Rule Check (DRC) violation location.

An implementation of John K. Outsterhout's Corner Stiching.

Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the congestion location.

A Java-based EDA tool for analogue integrated circuit design

Web EDA 🍃

Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction

A list of International Conferences on Integrated Circuit

Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits

This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.

Flora is an new GNN-based Open Source tool can apply to Dreamplace post-processing, so that can achieve faster and more accurate layout design.

Implementation of ROBDD in python

Covers the DEEDS training material for electronic Design

A standalone structural (gate-level) verilog parser

A repository for research contests spanning topics from hardware security and embedded/VLSI machine learning to electronic design automation, bio design automation, and formal verification.