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Verilog 166 322
Verilog 39 89
Python 34 26
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog 255 64
C 28 40
Forked from efabless/caravel_openframe_project
Example digital project for the Efabless Caravel "openframe" harness
Verilog 3 2
Repository to store metric results for OpenLane 2.0.0+
The next generation of OpenLane, rewritten from scratch with a modular architecture
Open-source IPs Package Manager (IPM)
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