Cross-platform CLI and Python drivers for AIO liquid coolers and other devices

**No Longer Maintained** Official RAMCloud repo

DRAMSim2: A cycle accurate DRAM simulator

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

MCMC toolbox for Matlab

Generic FPGA SDRAM controller, originally made for AS4C4M16SA

DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf

A 1MB chip RAM expansion for the A500+

Sample Arduino program to test 4164 DRAM chips.

BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are used for DRAM on-die ECC but can be extended to apply to other linear block codes (e.g., BCH, Reed-Solomon). BEER is described in the 2020 MICRO paper by Patel et al.: https://arxiv.org/abs/2009.07985.

A High-Level DRAM Timing, Power and Area Exploration Tool

A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.

Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omu…

Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.

DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.

HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/210…

Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.

Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]

REGA Model (REM), an accurate DRAM model.

Commodore C386SX-LT 2MB memory module schematics